existing.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* Append Mode (should throw exception)
******************************************************************************
Contents of existing_design.leaf.netlist
    Contents of TOP module leaf
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)



Caught exception: Design existing_design.existing.netlist exists. Cannot overwrite existing design data by default
******************************************************************************
* Overwrite Mode
******************************************************************************
******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of existing_design.leaf.netlist
    Contents of TOP module leaf
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)



Contents of existing_design.existing.netlist
    Contents of TOP module existing
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 't' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		't'
        	Position:	2
            Term: 'aux' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'aux'
        	Position:	3
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)
            Net: 't' (ModScalarNet)
            Net: 'aux' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		extra
        	LibName:		existing_design
        	CellName:		leaf
        	ViewName:		netlist
        	Master Cell Name:	leaf
        	NumBits:		1
        ModInstTerm:
        	Net:	in
        	Inst:	extra
	Posit:	0 (bound to 'in')
        ModInstTerm:
        	Net:	out
        	Inst:	extra
	Posit:	1 (bound to 'out')



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Info: The top module is existing
Contents of existing_designEMH.existing.netlist
    Contents of module leaf
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Net: 'out' (ModScalarNet)
            Net: 'in' (ModScalarNet)
    Contents of TOP module existing
            Term: 'aux' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'aux'
        	Position:	3
            Term: 't' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		't'
        	Position:	2
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Net: 'aux' (ModScalarNet)
            Net: 't' (ModScalarNet)
            Net: 'out' (ModScalarNet)
            Net: 'in' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		extra
        	Master Cell Name:	leaf
        	NumBits:		1
        ModInstTerm:
        	Net:	out
        	Inst:	extra
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	in
        	Inst:	extra
	Posit:	0 (bound to 'in')



Reader succeeded