assign.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of assign_design.assignTestSimple.netlist
    Contents of TOP module assignTestSimple
            Net: 'a' (ModScalarNet)
                Equiv:	b
            Net: 'b' (ModScalarNet)
                Equiv:	a



Contents of assign_design.assignTestPort.netlist
    Contents of TOP module assignTestPort
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Net: 'a' (ModScalarNet)
                Equiv:	b
            Net: 'b' (ModScalarNet)
                Equiv:	a



Contents of assign_design.assignTestBus.netlist
    Contents of TOP module assignTestBus
            Term: 'a[7:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	8
        	Net:		'a[7:0]'
        	Position:	0
            Net: 'a[7:0]' (ModBusNet)
            Net: 'a[7]' (ModBusNetBit)
                Equiv:	b[7]
            Net: 'a[6]' (ModBusNetBit)
                Equiv:	b[6]
            Net: 'a[5]' (ModBusNetBit)
                Equiv:	b[5]
            Net: 'a[4]' (ModBusNetBit)
                Equiv:	b[4]
            Net: 'a[3]' (ModBusNetBit)
                Equiv:	b[3]
            Net: 'a[2]' (ModBusNetBit)
                Equiv:	b[2]
            Net: 'a[1]' (ModBusNetBit)
                Equiv:	b[1]
            Net: 'a[0]' (ModBusNetBit)
                Equiv:	b[0]
            Net: 'b[7:0]' (ModBusNet)
            Net: 'b[7]' (ModBusNetBit)
                Equiv:	a[7]
            Net: 'b[6]' (ModBusNetBit)
                Equiv:	a[6]
            Net: 'b[5]' (ModBusNetBit)
                Equiv:	a[5]
            Net: 'b[4]' (ModBusNetBit)
                Equiv:	a[4]
            Net: 'b[3]' (ModBusNetBit)
                Equiv:	a[3]
            Net: 'b[2]' (ModBusNetBit)
                Equiv:	a[2]
            Net: 'b[1]' (ModBusNetBit)
                Equiv:	a[1]
            Net: 'b[0]' (ModBusNetBit)
                Equiv:	a[0]



Contents of assign_design.assignTestBundle.netlist
    Contents of TOP module assignTestBundle
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Net: 'a[1:0]' (ModBusNet)
            Net: 'a[1]' (ModBusNetBit)
                Equiv:	b, tie0
            Net: 'a[0]' (ModBusNetBit)
                Equiv:	c, tie1
            Net: 'b' (ModScalarNet)
                Equiv:	tie0, a[1]
            Net: 'c' (ModScalarNet)
                Equiv:	tie1, a[0]
            Net: 'b,c' (ModBundleNet)
            Net: 'tie0,tie1' (ModBundleNet)
            Net: 'tie0' (ModScalarNet)
            SigType:	tieLo
            Global:	true
                Equiv:	a[1], b
            Net: 'tie1' (ModScalarNet)
            SigType:	tieHi
            Global:	true
                Equiv:	a[0], c



Contents of assign_design.assignTestRegister.netlist
    Contents of TOP module assignTestRegister
            Term: 'in1' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in1'
        	Position:	0
            Term: 'in2' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in2'
        	Position:	1
            Term: 'in3[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'in3[1:0]'
        	Position:	2
            Term: 'in4[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'in4[1:0]'
        	Position:	3
            Term: 'in5[2:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	3
        	Net:		'in5[2:0]'
        	Position:	4
            Term: 'in6[2:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	3
        	Net:		'in6[2:0]'
        	Position:	5
            Term: 'out1' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out1'
        	Position:	6
            Term: 'out2[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out2[1:0]'
        	Position:	7
            Term: 'out3[2:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	3
        	Net:		'out3[2:0]'
        	Position:	8
            Net: 'in1' (ModScalarNet)
            Net: 'in2' (ModScalarNet)
            Net: 'in3[1:0]' (ModBusNet)
            Net: 'in4[1:0]' (ModBusNet)
            Net: 'in5[2:0]' (ModBusNet)
            Net: 'in6[2:0]' (ModBusNet)
            Net: 'out1' (ModScalarNet)
                Equiv:	reg1
            Net: 'out2[1:0]' (ModBusNet)
            Net: 'out2[1]' (ModBusNetBit)
                Equiv:	reg2[1]
            Net: 'out2[0]' (ModBusNetBit)
                Equiv:	reg2[0]
            Net: 'out3[2:0]' (ModBusNet)
            Net: 'out3[2]' (ModBusNetBit)
                Equiv:	reg3[2]
            Net: 'out3[1]' (ModBusNetBit)
                Equiv:	reg3[1]
            Net: 'out3[0]' (ModBusNetBit)
                Equiv:	reg3[0]
            Net: 'reg1' (ModScalarNet)
                Equiv:	out1
            Net: 'reg2[1:0]' (ModBusNet)
            Net: 'reg2[1]' (ModBusNetBit)
                Equiv:	out2[1]
            Net: 'reg2[0]' (ModBusNetBit)
                Equiv:	out2[0]
            Net: 'reg3[2:0]' (ModBusNet)
            Net: 'reg3[2]' (ModBusNetBit)
                Equiv:	out3[2]
            Net: 'reg3[1]' (ModBusNetBit)
                Equiv:	out3[1]
            Net: 'reg3[0]' (ModBusNetBit)
                Equiv:	out3[0]



Contents of assign_design.assignConst.netlist
    Contents of TOP module assignConst
            Net: 'n[1:0]' (ModBusNet)
            Net: 'n[1]' (ModBusNetBit)
                Equiv:	tie0
            Net: 'n[0]' (ModBusNetBit)
                Equiv:	tie1
            Net: 'tie1' (ModScalarNet)
            SigType:	tieHi
            Global:	true
                Equiv:	n[0]
            Net: 'tie0' (ModScalarNet)
            SigType:	tieLo
            Global:	true
                Equiv:	n[1]



Contents of assign_design.top.netlist
    Contents of TOP module top
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		assign_design
        	CellName:		assignTestSimple
        	ViewName:		netlist
        	Master Cell Name:	assignTestSimple
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	LibName:		assign_design
        	CellName:		assignTestPort
        	ViewName:		netlist
        	Master Cell Name:	assignTestPort
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	LibName:		assign_design
        	CellName:		assignTestBus
        	ViewName:		netlist
        	Master Cell Name:	assignTestBus
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I4
        	LibName:		assign_design
        	CellName:		assignTestBundle
        	ViewName:		netlist
        	Master Cell Name:	assignTestBundle
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I5
        	LibName:		assign_design
        	CellName:		assignTestRegister
        	ViewName:		netlist
        	Master Cell Name:	assignTestRegister
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I6
        	LibName:		assign_design
        	CellName:		assignConst
        	ViewName:		netlist
        	Master Cell Name:	assignConst
        	NumBits:		1



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Info: The top module is top
Contents of assign_designEMH.top.netlist
    Contents of module assignTestSimple
            Net: 'b' (ModScalarNet)
                Equiv:	a
            Net: 'a' (ModScalarNet)
                Equiv:	b
    Contents of module assignTestPort
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Net: 'b' (ModScalarNet)
                Equiv:	a
            Net: 'a' (ModScalarNet)
                Equiv:	b
    Contents of module assignTestBus
            Term: 'a[7:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	8
        	Net:		'a[7:0]'
        	Position:	0
            Net: 'b[0]' (ModBusNetBit)
                Equiv:	a[0]
            Net: 'b[1]' (ModBusNetBit)
                Equiv:	a[1]
            Net: 'b[2]' (ModBusNetBit)
                Equiv:	a[2]
            Net: 'b[3]' (ModBusNetBit)
                Equiv:	a[3]
            Net: 'b[4]' (ModBusNetBit)
                Equiv:	a[4]
            Net: 'b[5]' (ModBusNetBit)
                Equiv:	a[5]
            Net: 'b[6]' (ModBusNetBit)
                Equiv:	a[6]
            Net: 'b[7]' (ModBusNetBit)
                Equiv:	a[7]
            Net: 'b[7:0]' (ModBusNet)
            Net: 'a[0]' (ModBusNetBit)
                Equiv:	b[0]
            Net: 'a[1]' (ModBusNetBit)
                Equiv:	b[1]
            Net: 'a[2]' (ModBusNetBit)
                Equiv:	b[2]
            Net: 'a[3]' (ModBusNetBit)
                Equiv:	b[3]
            Net: 'a[4]' (ModBusNetBit)
                Equiv:	b[4]
            Net: 'a[5]' (ModBusNetBit)
                Equiv:	b[5]
            Net: 'a[6]' (ModBusNetBit)
                Equiv:	b[6]
            Net: 'a[7]' (ModBusNetBit)
                Equiv:	b[7]
            Net: 'a[7:0]' (ModBusNet)
    Contents of module assignTestBundle
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Net: 'tie1' (ModScalarNet)
            SigType:	tieHi
            Global:	true
                Equiv:	a[0], c
            Net: 'tie0' (ModScalarNet)
            SigType:	tieLo
            Global:	true
                Equiv:	a[1], b
            Net: 'tie0,tie1' (ModBundleNet)
            Net: 'b,c' (ModBundleNet)
            Net: 'c' (ModScalarNet)
                Equiv:	tie1, a[0]
            Net: 'b' (ModScalarNet)
                Equiv:	tie0, a[1]
            Net: 'a[0]' (ModBusNetBit)
                Equiv:	c, tie1
            Net: 'a[1]' (ModBusNetBit)
                Equiv:	b, tie0
            Net: 'a[1:0]' (ModBusNet)
    Contents of module assignTestRegister
            Term: 'out3[2:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	3
        	Net:		'out3[2:0]'
        	Position:	8
            Term: 'out2[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out2[1:0]'
        	Position:	7
            Term: 'out1' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out1'
        	Position:	6
            Term: 'in6[2:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	3
        	Net:		'in6[2:0]'
        	Position:	5
            Term: 'in5[2:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	3
        	Net:		'in5[2:0]'
        	Position:	4
            Term: 'in4[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'in4[1:0]'
        	Position:	3
            Term: 'in3[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'in3[1:0]'
        	Position:	2
            Term: 'in2' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in2'
        	Position:	1
            Term: 'in1' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in1'
        	Position:	0
            Net: 'reg3[0]' (ModBusNetBit)
                Equiv:	out3[0]
            Net: 'reg3[1]' (ModBusNetBit)
                Equiv:	out3[1]
            Net: 'reg3[2]' (ModBusNetBit)
                Equiv:	out3[2]
            Net: 'reg3[2:0]' (ModBusNet)
            Net: 'reg2[0]' (ModBusNetBit)
                Equiv:	out2[0]
            Net: 'reg2[1]' (ModBusNetBit)
                Equiv:	out2[1]
            Net: 'reg2[1:0]' (ModBusNet)
            Net: 'reg1' (ModScalarNet)
                Equiv:	out1
            Net: 'out3[0]' (ModBusNetBit)
                Equiv:	reg3[0]
            Net: 'out3[1]' (ModBusNetBit)
                Equiv:	reg3[1]
            Net: 'out3[2]' (ModBusNetBit)
                Equiv:	reg3[2]
            Net: 'out3[2:0]' (ModBusNet)
            Net: 'out2[0]' (ModBusNetBit)
                Equiv:	reg2[0]
            Net: 'out2[1]' (ModBusNetBit)
                Equiv:	reg2[1]
            Net: 'out2[1:0]' (ModBusNet)
            Net: 'out1' (ModScalarNet)
                Equiv:	reg1
            Net: 'in6[2:0]' (ModBusNet)
            Net: 'in5[2:0]' (ModBusNet)
            Net: 'in4[1:0]' (ModBusNet)
            Net: 'in3[1:0]' (ModBusNet)
            Net: 'in2' (ModScalarNet)
            Net: 'in1' (ModScalarNet)
    Contents of module assignConst
            Net: 'tie0' (ModScalarNet)
            SigType:	tieLo
            Global:	true
                Equiv:	n[1]
            Net: 'tie1' (ModScalarNet)
            SigType:	tieHi
            Global:	true
                Equiv:	n[0]
            Net: 'n[0]' (ModBusNetBit)
                Equiv:	tie1
            Net: 'n[1]' (ModBusNetBit)
                Equiv:	tie0
            Net: 'n[1:0]' (ModBusNet)
    Contents of TOP module top
        ModInst:
        	Is Bound:		yes
        	InstName:		I6
        	Master Cell Name:	assignConst
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I5
        	Master Cell Name:	assignTestRegister
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I4
        	Master Cell Name:	assignTestBundle
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	Master Cell Name:	assignTestBus
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	Master Cell Name:	assignTestPort
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	assignTestSimple
        	NumBits:		1



Reader succeeded