leaf.v

openaccess与verilog互相转化时所用的源代码

// Test the reader's ability to instantiate external cells (leaf cells).  The
// scalarLeaf module is a fully-defined external module that does not appear
// in the Verilog input.  The noOrder module is an external module that does
// not have terminal ordering information, however it is defined within the
// Verilog input and it has hierarchy.  The blackBox module is similar to the 
// noOrder module except that it does not have hierarchy and there is no
// valid view defined for the blackBox module.  The incomplete module has
// the "in" and "out" terminals defined and ordered but the "aux" terminal
// does not have order.  The noTop module does not have a top module defined.



module top();
    wire            a, b, c;
    wire    [0:1]   x;
    
    scalarLeaf  I1(a, b),
                I2(.in(b), .out(a));
    noOrder     I3(a, b);
    blackBox1   I4(a, b);
    blackBox2   I5(a, b);
    incomplete  I6(a, b, c);
    busLeaf     I7(.Q(x)),
                I9(.Q({n1, n2}));
    busLeaf2    I10(x);
    noTop	I11(.in(a), .out(b));
    blackBox3	I12(.in(a), .out(b));
endmodule


module incomplete(input in, output out, inout aux);
    blackBox1 I0(in, out);
endmodule



module noOrder(.in(x), .out(y));
    input   x;
    output  y;
    blackBox1 I0(x, y);
endmodule



module blackBox1(input in, output out);
endmodule



module blackBox2(.in(x), .out(y));
    input   x;
    output  y;
endmodule



module busLeaf2(Q);
    inout   [1:0] Q;
endmodule