pcr782725.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of pcr782725_design.top.netlist
    Contents of TOP module top
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'outvcc1' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'outvcc1'
        	Position:	2
            Term: 'outvcc2' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'outvcc2'
        	Position:	3
            Term: 'outvccbus[1:3]' (ModBusTerm)
        	TermType:	output
        	NumBits:	3
        	Net:		'outvccbus[1:3]'
        	Position:	4
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)
            Net: 'outvcc1' (ModScalarNet)
            SigType:	tieHi
            Net: 'outvcc2' (ModScalarNet)
                Equiv:	outvccbus[3], vcc2, vccbus[3], tie1
            Net: 'outvccbus[1:3]' (ModBusNet)
            Net: 'outvccbus[2]' (ModBusNetBit)
            SigType:	tieHi
            Net: 'outvccbus[3]' (ModBusNetBit)
                Equiv:	vcc2, vccbus[3], tie1, outvcc2
            Net: 'vccbus[1:3]' (ModBusNet)
            Net: 'vccbus[2]' (ModBusNetBit)
            SigType:	tieHi
            Net: 'vccbus[3]' (ModBusNetBit)
                Equiv:	tie1, outvcc2, outvccbus[3], vcc2
            Net: 'tie1' (ModScalarNet)
            SigType:	tieHi
            Global:	true
                Equiv:	outvcc2, outvccbus[3], vcc2, vccbus[3]
            Net: 'vcc1' (ModScalarNet)
            SigType:	tieHi
            Net: 'vcc2' (ModScalarNet)
                Equiv:	vccbus[3], tie1, outvcc2, outvccbus[3]



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Info: The top module is top
Contents of pcr782725_designEMH.top.netlist
    Contents of TOP module top
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'outvcc1' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'outvcc1'
        	Position:	2
            Term: 'outvcc2' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'outvcc2'
        	Position:	3
            Term: 'outvccbus[1:3]' (ModBusTerm)
        	TermType:	output
        	NumBits:	3
        	Net:		'outvccbus[1:3]'
        	Position:	4
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)
            Net: 'outvcc1' (ModScalarNet)
            SigType:	tieHi
            Net: 'outvcc2' (ModScalarNet)
                Equiv:	outvccbus[3], vcc2, vccbus[3], tie1
            Net: 'outvccbus[1:3]' (ModBusNet)
            Net: 'outvccbus[2]' (ModBusNetBit)
            SigType:	tieHi
            Net: 'outvccbus[3]' (ModBusNetBit)
                Equiv:	vcc2, vccbus[3], tie1, outvcc2
            Net: 'vccbus[1:3]' (ModBusNet)
            Net: 'vccbus[2]' (ModBusNetBit)
            SigType:	tieHi
            Net: 'vccbus[3]' (ModBusNetBit)
                Equiv:	tie1, outvcc2, outvccbus[3], vcc2
            Net: 'tie1' (ModScalarNet)
            SigType:	tieHi
            Global:	true
                Equiv:	outvcc2, outvccbus[3], vcc2, vccbus[3]
            Net: 'vcc1' (ModScalarNet)
            SigType:	tieHi
            Net: 'vcc2' (ModScalarNet)
                Equiv:	vccbus[3], tie1, outvcc2, outvccbus[3]



Reader succeeded