detecttop.v

openaccess与verilog互相转化时所用的源代码

// Test top module detection.  Both modules "candidateTop1" and "candidateTop2"
// have no references to them in this design.  Both candidates have the same
// hierarchical depth, and even share a module "shared".  The "candidateTop1"
// module has more "width" than "candidateTop2" but "candidateTop2" appears
// later in the Verilog input.  Neither candidate appears last in the file.
// The expectation is that "candidateTop2" will be selected as the top module
// and the modules "remove1" and "remove2" should be removed from the design.

module remove1(inout io);
endmodule

module remove2(inout io);
    remove1 I5(io);
endmodule

module keep2(inout io);
    keep1   I3(io),
            I4(io);
endmodule

module shared(inout io);
endmodule

module candidateTop1(inout io);
    shared  I6(io);
    remove2 I7(io),
            I8(io),
            I9(io),
            I10(io),
            I11(io);
endmodule

module  candidateTop2(inout io);
    keep2   I1(io);
    shared  I2(io);
endmodule

module keep1(inout io);
endmodule