📄 datatype.ref
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Inst: order_supply Posit: 0 (bound to 'in')Contents of dataType_design.top.netlist Contents of TOP module top ModInst: Is Bound: yes InstName: I1 LibName: dataType_design CellName: wireTest ViewName: netlist Master Cell Name: wireTest NumBits: 1 ModInst: Is Bound: yes InstName: I2 LibName: dataType_design CellName: triTest ViewName: netlist Master Cell Name: triTest NumBits: 1 ModInst: Is Bound: yes InstName: I3 LibName: dataType_design CellName: supplyTest ViewName: netlist Master Cell Name: supplyTest NumBits: 1Reader succeeded******************************************************************************* No Explode, EMH******************************************************************************Warning: Always blocks are not implementedInfo: The top module is topContents of dataType_designEMH.top.netlist Contents of module scalar Term: 'out' (ModScalarTerm) TermType: output NumBits: 1 Net: 'out' Position: 1 Term: 'in' (ModScalarTerm) TermType: input NumBits: 1 Net: 'in' Position: 0 Net: 'out' (ModScalarNet) Net: 'in' (ModScalarNet) Contents of module wireTest Net: 'wor_b' (ModScalarNet) Net: 'wor_a' (ModScalarNet) Net: 'wand_b' (ModScalarNet) Net: 'wand_a' (ModScalarNet) Net: 'wire_b' (ModScalarNet) Net: 'wire_a' (ModScalarNet) ModInst: Is Bound: yes InstName: named_wor Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_wor Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: named_wand Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_wand Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: named_wire Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_wire Master Cell Name: scalar NumBits: 1 ModInstTerm: Net: wor_b Inst: named_wor Term: out (bound to 'out') ModInstTerm: Net: wor_b Inst: order_wor Posit: 1 (bound to 'out') ModInstTerm: Net: wor_a Inst: named_wor Term: in (bound to 'in') ModInstTerm: Net: wor_a Inst: order_wor Posit: 0 (bound to 'in') ModInstTerm: Net: wand_b Inst: named_wand Term: out (bound to 'out') ModInstTerm: Net: wand_b Inst: order_wand Posit: 1 (bound to 'out') ModInstTerm: Net: wand_a Inst: named_wand Term: in (bound to 'in') ModInstTerm: Net: wand_a Inst: order_wand Posit: 0 (bound to 'in') ModInstTerm: Net: wire_b Inst: named_wire Term: out (bound to 'out') ModInstTerm: Net: wire_b Inst: order_wire Posit: 1 (bound to 'out') ModInstTerm: Net: wire_a Inst: named_wire Term: in (bound to 'in') ModInstTerm: Net: wire_a Inst: order_wire Posit: 0 (bound to 'in') Contents of module triTest Net: 'tri1_b' (ModScalarNet) Net: 'tri1_a' (ModScalarNet) Net: 'tri0_b' (ModScalarNet) Net: 'tri0_a' (ModScalarNet) Net: 'trior_b' (ModScalarNet) Net: 'trior_a' (ModScalarNet) Net: 'triand_b' (ModScalarNet) Net: 'triand_a' (ModScalarNet) Net: 'tri_b' (ModScalarNet) Net: 'tri_a' (ModScalarNet) ModInst: Is Bound: yes InstName: named_tri1 Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_tri1 Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: named_tri0 Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_tri0 Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: named_trior Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_trior Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: named_triand Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_triand Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: named_tri Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_tri Master Cell Name: scalar NumBits: 1 ModInstTerm: Net: tri1_b Inst: named_tri1 Term: out (bound to 'out') ModInstTerm: Net: tri1_b Inst: order_tri1 Posit: 1 (bound to 'out') ModInstTerm: Net: tri1_a Inst: named_tri1 Term: in (bound to 'in') ModInstTerm: Net: tri1_a Inst: order_tri1 Posit: 0 (bound to 'in') ModInstTerm: Net: tri0_b Inst: named_tri0 Term: out (bound to 'out') ModInstTerm: Net: tri0_b Inst: order_tri0 Posit: 1 (bound to 'out') ModInstTerm: Net: tri0_a Inst: named_tri0 Term: in (bound to 'in') ModInstTerm: Net: tri0_a Inst: order_tri0 Posit: 0 (bound to 'in') ModInstTerm: Net: trior_b Inst: named_trior Term: out (bound to 'out') ModInstTerm: Net: trior_b Inst: order_trior Posit: 1 (bound to 'out') ModInstTerm: Net: trior_a Inst: named_trior Term: in (bound to 'in') ModInstTerm: Net: trior_a Inst: order_trior Posit: 0 (bound to 'in') ModInstTerm: Net: triand_b Inst: named_triand Term: out (bound to 'out') ModInstTerm: Net: triand_b Inst: order_triand Posit: 1 (bound to 'out') ModInstTerm: Net: triand_a Inst: named_triand Term: in (bound to 'in') ModInstTerm: Net: triand_a Inst: order_triand Posit: 0 (bound to 'in') ModInstTerm: Net: tri_b Inst: named_tri Term: out (bound to 'out') ModInstTerm: Net: tri_b Inst: order_tri Posit: 1 (bound to 'out') ModInstTerm: Net: tri_a Inst: named_tri Term: in (bound to 'in') ModInstTerm: Net: tri_a Inst: order_tri Posit: 0 (bound to 'in') Contents of module supplyTest Net: 'vdd' (ModScalarNet) SigType: tieHi Net: 'gnd' (ModScalarNet) SigType: tieLo ModInst: Is Bound: yes InstName: named_supply Master Cell Name: scalar NumBits: 1 ModInst: Is Bound: yes InstName: order_supply Master Cell Name: scalar NumBits: 1 ModInstTerm: Net: vdd Inst: named_supply Term: in (bound to 'in') ModInstTerm: Net: vdd Inst: order_supply Posit: 0 (bound to 'in') ModInstTerm: Net: gnd Inst: named_supply Term: out (bound to 'out') ModInstTerm: Net: gnd Inst: order_supply Posit: 1 (bound to 'out') Contents of TOP module top ModInst: Is Bound: yes InstName: I3 Master Cell Name: supplyTest NumBits: 1 ModInst: Is Bound: yes InstName: I2 Master Cell Name: triTest NumBits: 1 ModInst: Is Bound: yes InstName: I1 Master Cell Name: wireTest NumBits: 1Reader succeeded⌨️ 快捷键说明
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