termnotfoundleaf3.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 18 行

// Test the reader's ability to detect an extra terminal in the leaf cell's
// declaration.



module scalarLeaf(.in(x), .out(y));
    input   in;
    output  out;
    wire    x, y;
endmodule



module top3();
    scalarLeaf  I1(a, b, c);
endmodule