connect.v

openaccess与verilog互相转化时所用的源代码

module scalarLeaf(scalarIn, scalarOut);
	input 	scalarIn;
	output  scalarOut;
endmodule

module twoBusLeaf(busIn, busOut);
	input  [1:0] busIn;
	output [1:0] busOut;
endmodule

module scalarAndBusLeaf(scalarIn, busOut);
	input        scalarIn;
	output [1:0] busOut;
endmodule

module top (); 
	wire 		a;
	reg		b;
	wire		c;
	reg	        d;
	wire    [1:0]   e;
	reg     [1:0]   f;

	scalarLeaf // test scalar term connectivity 
	  s0(b,a),                               // scalar to scalar by order
	  s1(e[1],f[0]),                         // bus bit to scalar by order
	  s2(.scalarIn(a), .scalarOut(b)),       // scalar to scalar by name
	  s3(.scalarIn(e[0]), .scalarOut(f[1])); // bus bit to scalar by name
	
	twoBusLeaf // test bus term connectivity
          tb1(.busIn({a,b}),.busOut({c,d})),     // scalar to bus by name
          tb2(e,f),                              // bus to bus by order
          tb3(.busIn(e),.busOut(f));             // bus to bus by name

	scalarAndBusLeaf // mixing scalar and bus terms
          sb0(b,e), // scalar to scalar and bus to bus (like-to-like) by order
	  sb1(.scalarIn(b),.busOut(e)),      // like-to-like by name
          sb2(e[0],f),                       // bus bit and bus by order
          sb3(.scalarIn(e[0]),.busOut(f)),   // bus bit and bus by name
	  sb5(.scalarIn(a),.busOut({b,c}));  // all scalars by name
endmodule