width.ref

openaccess与verilog互相转化时所用的源代码

            Net: 'p[31:0]' (ModBusNet)
            Net: 'z[15:0]' (ModBusNet)
            Net: 'y' (ModScalarNet)
            Net: 'x' (ModScalarNet)
            Net: 'e' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'a[3:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I20
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I19
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I18
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I17
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I16
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I15
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I14
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I13
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I12
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I11
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I30
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I29
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I10
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I09
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I28
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I27
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I08
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I07
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I26
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I25
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I06
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I05
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I24
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I23
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I04
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I03
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I22
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I21
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I02
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I01
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn19_[11:0]
        	Inst:	I13
        	Term:	in[0:15] (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn18_[11:0]
        	Inst:	I14
        	Term:	in[0:15] (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn17_[11:0]
        	Inst:	I15
	Posit:	0 (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn16_[11:0]
        	Inst:	I16
	Posit:	0 (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	b,13*c,d,UNCONNECTED_oaVerilogIn15_
        	Inst:	I20
        	Term:	in[0:15] (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn14_[11:0],a[3:0]
        	Inst:	I09
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn13_[11:0],b,c,d,e
        	Inst:	I10
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	p[15:0]
        	Inst:	I29
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	b,15*c
        	Inst:	I30
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn12_[11:0],a[3:0]
        	Inst:	I11
	Posit:	0 (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn11_[11:0],b,c,d,e
        	Inst:	I12
	Posit:	0 (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn10_,b,13*c,d
        	Inst:	I19
	Posit:	0 (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	b,5*c,d,UNCONNECTED_oaVerilogIn9_
        	Inst:	I18
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn8_,b,5*c,d
        	Inst:	I17
	Posit:	0 (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn7_[3:0]
        	Inst:	I08
	Posit:	0 (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn6_[3:0]
        	Inst:	I07
	Posit:	0 (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn5_[3:0]
        	Inst:	I06
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn4_[3:0]
        	Inst:	I05
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn3_[3:0],b,c,d,e
        	Inst:	I04
	Posit:	0 (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn2_[3:0],a[3:0]
        	Inst:	I03
	Posit:	0 (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I28
	Posit:	0 (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I26
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I24
	Posit:	0 (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I22
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I27
	Posit:	0 (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I25
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I23
	Posit:	0 (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I21
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn1_[3:0],b,c,d,e
        	Inst:	I02
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn0_[3:0],a[3:0]
        	Inst:	I01
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	y
        	Inst:	I19
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I17
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I16
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I14
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I12
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I10
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I08
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I06
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I04
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I02
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I20
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I18
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I15
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I13
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I11
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I30
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I29
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I09
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I28
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I27
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I07
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I26
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I25
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I05
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I24
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I23
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I03
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I22
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I21
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I01
        	Term:	out (bound to 'out')
    Contents of module D16BB
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'in[15:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	16
        	Net:		'in[15:0]'
        	Position:	0
            Net: 'out' (ModScalarNet)
            Net: 'in[15:0]' (ModBusNet)
    Contents of module A16BB
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'in[0:15]' (ModBusTerm)
        	TermType:	input
        	NumBits:	16
        	Net:		'in[0:15]'
        	Position:	0
            Net: 'out' (ModScalarNet)
            Net: 'in[0:15]' (ModBusNet)



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