width.ref

openaccess与verilog互相转化时所用的源代码

        	ViewName:		netlist
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I14
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		netlist
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I15
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		netlist
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I16
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		netlist
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I17
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I18
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I19
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I20
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		netlist
        	Master Cell Name:	A16BB
        	NumBits:		1
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I15
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I11
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I07
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I03
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	x
        	Inst:	I20
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I18
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I15
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I13
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I11
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I30
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I29
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I09
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I28
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I27
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I07
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I26
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I25
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I05
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I24
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I23
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I03
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I22
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I21
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I01
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I19
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I17
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I16
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I14
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I12
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I10
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I08
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I06
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I04
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I02
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	z[15:0]
        	Inst:	I27
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	z[15:0]
        	Inst:	I23
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn0_[3:0],a[3:0]
        	Inst:	I01
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I16
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I12
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I08
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I04
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn1_[3:0],b,c,d,e
        	Inst:	I02
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I25
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I21
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,14*c,d
        	Inst:	I28
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,14*c,d
        	Inst:	I24
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I26
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I22
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn2_[3:0]
        	Inst:	I05
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn3_[3:0]
        	Inst:	I06
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,5*c,d
        	Inst:	I17
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,5*c,d,UNCONNECTED_oaVerilogIn4_
        	Inst:	I18
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,13*c,d
        	Inst:	I19
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,15*c
        	Inst:	I30
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	p[15:0]
        	Inst:	I29
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn5_[11:0],b,c,d,e
        	Inst:	I10
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn6_[11:0],a[3:0]
        	Inst:	I09
        	Term:	in[15:0] (bound to 'in[15:0]')
        ModInstTerm:
        	Net:	b,13*c,d,UNCONNECTED_oaVerilogIn7_
        	Inst:	I20
        	Term:	in[0:15] (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn8_[11:0]
        	Inst:	I14
        	Term:	in[0:15] (bound to 'in[0:15]')
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn9_[11:0]
        	Inst:	I13
        	Term:	in[0:15] (bound to 'in[0:15]')



Contents of width_design.A16BB.netlist
    Contents of TOP module A16BB
            Term: 'in[0:15]' (ModBusTerm)
        	TermType:	input
        	NumBits:	16
        	Net:		'in[0:15]'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Net: 'in[0:15]' (ModBusNet)
            Net: 'out' (ModScalarNet)



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Warning: The width of terminal "in[7:0]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "z[15:0]". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "{b,14*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "z[15:0]". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "{b,14*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "z[15:0]". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "{b,14*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "z[15:0]". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "{b,14*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[7:0]" does not match the width of net "{b,5*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[0:7]" does not match the width of net "{b,5*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "{b,13*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "{b,30*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "p[31:0]". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[0:15]" does not match the width of net "{b,13*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[0:15]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[0:15]" does not match the width of net "a[3:0]". Some bits are unconnected.
Warning: The width of terminal "in[0:15]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[0:15]" does not match the width of net "a[3:0]". Some bits are unconnected.
Info: The top module is top
Contents of width_designEMH.top.netlist
    Contents of module D8BB
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'in[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'in[7:0]'
        	Position:	0
            Net: 'out' (ModScalarNet)
            Net: 'in[7:0]' (ModBusNet)
    Contents of module A8BB
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'in[0:7]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'in[0:7]'
        	Position:	0
            Net: 'out' (ModScalarNet)
            Net: 'in[0:7]' (ModBusNet)
    Contents of TOP module top
            Net: 'a[3:0],UNCONNECTED_oaVerilogIn19_[11:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn19_[11:0]' (ModBusNet)
            Net: 'b,c,d,e,UNCONNECTED_oaVerilogIn18_[11:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn18_[11:0]' (ModBusNet)
            Net: 'a[3:0],UNCONNECTED_oaVerilogIn17_[11:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn17_[11:0]' (ModBusNet)
            Net: 'b,c,d,e,UNCONNECTED_oaVerilogIn16_[11:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn16_[11:0]' (ModBusNet)
            Net: 'b,13*c,d,UNCONNECTED_oaVerilogIn15_' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn15_' (ModScalarNet)
            Net: 'UNCONNECTED_oaVerilogIn14_[11:0],a[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn14_[11:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn13_[11:0],b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn13_[11:0]' (ModBusNet)
            Net: 'p[15:0]' (ModBusNet)
            Net: 'b,15*c' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn12_[11:0],a[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn12_[11:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn11_[11:0],b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn11_[11:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn10_,b,13*c,d' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn10_' (ModScalarNet)
            Net: 'b,13*c,d' (ModBundleNet)
            Net: 'b,5*c,d,UNCONNECTED_oaVerilogIn9_' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn9_' (ModScalarNet)
            Net: 'UNCONNECTED_oaVerilogIn8_,b,5*c,d' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn8_' (ModScalarNet)
            Net: 'b,5*c,d' (ModBundleNet)
            Net: 'b,30*c,d' (ModBundleNet)
            Net: 'b,c,d,e,UNCONNECTED_oaVerilogIn7_[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn7_[3:0]' (ModBusNet)
            Net: 'a[3:0],UNCONNECTED_oaVerilogIn6_[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn6_[3:0]' (ModBusNet)
            Net: 'b,c,d,e,UNCONNECTED_oaVerilogIn5_[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn5_[3:0]' (ModBusNet)
            Net: 'a[3:0],UNCONNECTED_oaVerilogIn4_[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn4_[3:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn3_[3:0],b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn3_[3:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn2_[3:0],a[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn2_[3:0]' (ModBusNet)
            Net: 'b,7*c' (ModBundleNet)
            Net: 'b,14*c,d' (ModBundleNet)
            Net: 'z[7:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn1_[3:0],b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn1_[3:0]' (ModBusNet)
            Net: 'b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn0_[3:0],a[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn0_[3:0]' (ModBusNet)