width.ref

openaccess与verilog互相转化时所用的源代码

        ModInstTerm:
        	Net:	y
        	Inst:	I06
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I04
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	y
        	Inst:	I02
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	z[15:0]
        	Inst:	I27
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	z[15:0]
        	Inst:	I23
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	p[31:0]
        	Inst:	I29
        	Term:	in[31:0] (not bound)
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn0_[3:0],a[3:0]
        	Inst:	I01
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I16
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I14
        	Term:	in[3:0] (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I12
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I10
        	Term:	in[3:0] (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I08
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,c,d,e
        	Inst:	I04
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	UNCONNECTED_oaVerilogIn1_[3:0],b,c,d,e
        	Inst:	I02
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I25
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	z[7:0]
        	Inst:	I21
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	b,14*c,d
        	Inst:	I28
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,14*c,d
        	Inst:	I24
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I26
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,7*c
        	Inst:	I22
        	Term:	in[7:0] (bound to 'in[7:0]')
        ModInstTerm:
        	Net:	a[3:0],UNCONNECTED_oaVerilogIn2_[3:0]
        	Inst:	I05
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,c,d,e,UNCONNECTED_oaVerilogIn3_[3:0]
        	Inst:	I06
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,30*c,d
        	Inst:	I30
        	Term:	in[31:0] (not bound)
        ModInstTerm:
        	Net:	b,5*c,d
        	Inst:	I17
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	b,5*c,d,UNCONNECTED_oaVerilogIn4_
        	Inst:	I18
        	Term:	in[0:7] (bound to 'in[0:7]')
        ModInstTerm:
        	Net:	b,13*c,d
        	Inst:	I20
        	Term:	in[14:0] (not bound)
        ModInstTerm:
        	Net:	b,13*c,d
        	Inst:	I19
	Posit:	0 (not bound)



Warning: The width of terminal "in[15:0]" does not match the width of net "{b,30*c,d}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "p[31:0]". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "{b,c,d,e}". Some bits are unconnected.
Warning: The width of terminal "in[15:0]" does not match the width of net "a[3:0]". Some bits are unconnected.
Contents of width_design.top.netlist
    Contents of TOP module top
            Net: 'a[3:0]' (ModBusNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'e' (ModScalarNet)
            Net: 'x' (ModScalarNet)
            Net: 'y' (ModScalarNet)
            Net: 'z[15:0]' (ModBusNet)
            Net: 'p[31:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn0_[3:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn0_[3:0],a[3:0]' (ModBundleNet)
            Net: 'b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn1_[3:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn1_[3:0],b,c,d,e' (ModBundleNet)
            Net: 'z[7:0]' (ModBusNet)
            Net: 'b,14*c,d' (ModBundleNet)
            Net: 'b,7*c' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn2_[3:0]' (ModBusNet)
            Net: 'a[3:0],UNCONNECTED_oaVerilogIn2_[3:0]' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn3_[3:0]' (ModBusNet)
            Net: 'b,c,d,e,UNCONNECTED_oaVerilogIn3_[3:0]' (ModBundleNet)
            Net: 'b,30*c,d' (ModBundleNet)
            Net: 'b,5*c,d' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn4_' (ModScalarNet)
            Net: 'b,5*c,d,UNCONNECTED_oaVerilogIn4_' (ModBundleNet)
            Net: 'b,13*c,d' (ModBundleNet)
            Net: 'b,15*c' (ModBundleNet)
            Net: 'p[15:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn5_[11:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn5_[11:0],b,c,d,e' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn6_[11:0]' (ModBusNet)
            Net: 'UNCONNECTED_oaVerilogIn6_[11:0],a[3:0]' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I01
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I02
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I21
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I22
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I03
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I04
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I23
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I24
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I05
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I06
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I25
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I26
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I07
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I08
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I27
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I28
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I09
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I10
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I29
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I30
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I11
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I12
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		I13
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		I14
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		I15
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		I16
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I17
        	LibName:		width_design
        	CellName:		D8BB
        	ViewName:		netlist
        	Master Cell Name:	D8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I18
        	LibName:		width_design
        	CellName:		A8BB
        	ViewName:		netlist
        	Master Cell Name:	A8BB
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I19
        	LibName:		width_design
        	CellName:		D16BB
        	ViewName:		netlist
        	Master Cell Name:	D16BB
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		I20
        	LibName:		width_design
        	CellName:		A16BB
        	ViewName:		abstract
        	NumBits:		1
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I15
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I13
        	Term:	in[3:0] (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I11
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I07
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	a[3:0]
        	Inst:	I03
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	x
        	Inst:	I20
        	Term:	out (not bound)
        ModInstTerm:
        	Net:	x
        	Inst:	I18
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I15
	Posit:	1 (not bound)
        ModInstTerm:
        	Net:	x
        	Inst:	I13
        	Term:	out (not bound)
        ModInstTerm:
        	Net:	x
        	Inst:	I11
	Posit:	1 (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I30
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x
        	Inst:	I29
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	x