stubtermwidth.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 13 行

// Verify that the reader will detect inconsistent terminal width
// specifications on stub modules.

module top();
    wire            wireToX, wireToZ;
    wire    [1:0]   busToY;
    wire    [2:0]   widerBusToY;
    
    stub   first(.x(wireToX), .y(busToY), .z(wireToZ)),
           second(.x(wireToX), .y(widerBusToY), .z(wireToZ));
endmodule