leafexplicit.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 12 行

// Test the reader's ability to instantiate external cells (leaf cells).



module top();
    wire a, b;
    scalarleaf  I1(a, b),
                I2(.in(b), .out(a));
endmodule