gaps.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 33 行

// Test support for gaps in both the port list declaration and in the
// connection list of the module instantiation.  The top module deliberately
// attempts to connect to the gap in the port list declaration and deliberately
// omits the connection to the bus port b of module bottom.



module bottom(a, b, {c,d},  , f); 
    inout a, c, d, f;
    inout [1:0] b;
endmodule



module mid(a, b, c);
    inout [1:0] a;
    inout [1:0] b;
    inout c;
endmodule



module top();
    wire [1:0] A, K, P, T, B, F, Q, U;
    bottom I1( , A, B, C, D),
           I2(E,  , F, G, H),
           I3(J, K,  , L, M),
           I4(N, P, Q,  , R),
           I5(S, T, U, V,  ); 
           
    mid I6( , , W);
endmodule