multifile1.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 7 行

// This is the first of three files in the multiFile test.

module level1(l1_in, l1_out);
	input  [7:0] l1_in;
	output l1_out;
endmodule