arrayinst.ref

openaccess与verilog互相转化时所用的源代码

Contents of arrayInstRefLib.leafCell.abstract
    Contents of TOP module leafCell
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out[1:0]'
        	Position:	1
            Net: 'in' (ModScalarNet)
            Net: 'out[1:0]' (ModBusNet)



******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of arrayInst_design.dff.netlist
    Contents of TOP module dff
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	0
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	1
            Term: 'rst' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'rst'
        	Position:	2
            Term: 'clk' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'clk'
        	Position:	3
            Net: 'out' (ModScalarNet)
            Net: 'in' (ModScalarNet)
            Net: 'rst' (ModScalarNet)
            Net: 'clk' (ModScalarNet)



Contents of arrayInst_design.oneBit.netlist
    Contents of TOP module oneBit
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		r[0]
        	LibName:		arrayInst_design
        	CellName:		dff
        	ViewName:		netlist
        	Master Cell Name:	dff
        	NumBits:		1
        ModInstTerm:
        	Net:	a
        	Inst:	r[0]
	Posit:	0 (bound to 'out')
        ModInstTerm:
        	Net:	b
        	Inst:	r[0]
	Posit:	1 (bound to 'in')
        ModInstTerm:
        	Net:	c
        	Inst:	r[0]
	Posit:	2 (bound to 'rst')
        ModInstTerm:
        	Net:	d
        	Inst:	r[0]
	Posit:	3 (bound to 'clk')



Contents of arrayInst_design.byName.netlist
    Contents of TOP module byName
            Term: 'Q[7:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	8
        	Net:		'Q[7:0]'
        	Position:	0
            Term: 'D[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'D[7:0]'
        	Position:	1
            Term: 'clear' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'clear'
        	Position:	2
            Term: 'clock' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'clock'
        	Position:	3
            Net: 'Q[7:0]' (ModBusNet)
            Net: 'D[7:0]' (ModBusNet)
            Net: 'clear' (ModScalarNet)
            Net: 'clock' (ModScalarNet)
            Net: '8*clear' (ModBundleNet)
            Net: '8*clock' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		r[7:0]
        	LibName:		arrayInst_design
        	CellName:		dff
        	ViewName:		netlist
        	Master Cell Name:	dff
        	NumBits:		8
        ModInstTerm:
        	Net:	Q[7:0]
        	Inst:	r[7:0]
        	Term:	out (bound to 'out')
        ModInstTerm:
        	Net:	D[7:0]
        	Inst:	r[7:0]
        	Term:	in (bound to 'in')
        ModInstTerm:
        	Net:	8*clear
        	Inst:	r[7:0]
        	Term:	rst (bound to 'rst')
        ModInstTerm:
        	Net:	8*clock
        	Inst:	r[7:0]
        	Term:	clk (bound to 'clk')



Contents of arrayInst_design.byOrder.netlist
    Contents of TOP module byOrder
            Term: 'Q[7:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	8
        	Net:		'Q[7:0]'
        	Position:	0
            Term: 'D[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'D[7:0]'
        	Position:	1
            Term: 'clear' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'clear'
        	Position:	2
            Term: 'clock' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'clock'
        	Position:	3
            Net: 'Q[7:0]' (ModBusNet)
            Net: 'D[7:0]' (ModBusNet)
            Net: 'clear' (ModScalarNet)
            Net: 'clock' (ModScalarNet)
            Net: '8*clock' (ModBundleNet)
            Net: '8*clear' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		r[7:0]
        	LibName:		arrayInst_design
        	CellName:		dff
        	ViewName:		netlist
        	Master Cell Name:	dff
        	NumBits:		8
        ModInstTerm:
        	Net:	Q[7:0]
        	Inst:	r[7:0]
	Posit:	0 (bound to 'out')
        ModInstTerm:
        	Net:	D[7:0]
        	Inst:	r[7:0]
	Posit:	1 (bound to 'in')
        ModInstTerm:
        	Net:	8*clock
        	Inst:	r[7:0]
	Posit:	2 (bound to 'rst')
        ModInstTerm:
        	Net:	8*clear
        	Inst:	r[7:0]
	Posit:	3 (bound to 'clk')



Contents of arrayInst_design.top.netlist
    Contents of TOP module top
            Net: 'a[15:0]' (ModBusNet)
            Net: 'b[15:0]' (ModBusNet)
            Net: 'c[15:0]' (ModBusNet)
            Net: 'd[15:0]' (ModBusNet)
            Net: 'A' (ModScalarNet)
            Net: 'B' (ModScalarNet)
            Net: 'C' (ModScalarNet)
            Net: 'D' (ModScalarNet)
            Net: 'E' (ModScalarNet)
            Net: 'F' (ModScalarNet)
            Net: 'G' (ModScalarNet)
            Net: 'H' (ModScalarNet)
            Net: 'J' (ModScalarNet)
            Net: 'K' (ModScalarNet)
            Net: 'P' (ModScalarNet)
            Net: 'Q' (ModScalarNet)
            Net: 'X' (ModScalarNet)
            Net: 'Y' (ModScalarNet)
            Net: 'bx[7:0]' (ModBusNet)
            Net: 'by[7:0]' (ModBusNet)
            Net: '2*P' (ModBundleNet)
            Net: '2*Q' (ModBundleNet)
            Net: 'bx[7],bx[6],bx[5],bx[4],bx[3],bx[2],bx[1],bx[0],bx[7],bx[6],bx[5],bx[4],bx[3],bx[2],bx[1],bx[0]' (ModBundleNet)
            Net: 'by[7],by[6],by[5],by[4],by[3],by[2],by[1],by[0],by[7],by[6],by[5],by[4],by[3],by[2],by[1],by[0]' (ModBundleNet)
            Net: '2*X' (ModBundleNet)
            Net: '2*Y' (ModBundleNet)
            Net: 'A,B,C,D,E,F,G,H,A,B,C,D,E,F,G,H' (ModBundleNet)
            Net: '2*J' (ModBundleNet)
            Net: '2*K' (ModBundleNet)
            Net: '4*A' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		name[1:0]
        	LibName:		arrayInst_design
        	CellName:		byName
        	ViewName:		netlist
        	Master Cell Name:	byName
        	NumBits:		2
        ModInst:
        	Is Bound:		yes
        	InstName:		name2[1:0]
        	LibName:		arrayInst_design
        	CellName:		byName
        	ViewName:		netlist
        	Master Cell Name:	byName
        	NumBits:		2
        ModInst:
        	Is Bound:		yes
        	InstName:		order[1:0]
        	LibName:		arrayInst_design
        	CellName:		byOrder
        	ViewName:		netlist
        	Master Cell Name:	byOrder
        	NumBits:		2
        ModInst:
        	Is Bound:		yes
        	InstName:		order2[1:0]
        	LibName:		arrayInst_design
        	CellName:		byOrder
        	ViewName:		netlist
        	Master Cell Name:	byOrder
        	NumBits:		2
        ModInst:
        	Is Bound:		yes
        	InstName:		bundle[1:0]
        	LibName:		arrayInst_design
        	CellName:		byOrder
        	ViewName:		netlist
        	Master Cell Name:	byOrder
        	NumBits:		2
        ModInst:
        	Is Bound:		yes
        	InstName:		name3[3:0]
        	LibName:		arrayInstRefLib
        	CellName:		leafCell
        	ViewName:		abstract
        	Master Cell Name:	leafCell
        	NumBits:		4
        ModInst:
        	Is Bound:		yes
        	InstName:		order3[3:0]
        	LibName:		arrayInstRefLib
        	CellName:		leafCell
        	ViewName:		abstract
        	Master Cell Name:	leafCell
        	NumBits:		4
        ModInstTerm:
        	Net:	a[15:0]
        	Inst:	name[1:0]
        	Term:	Q[7:0] (bound to 'Q[7:0]')
        ModInstTerm:
        	Net:	b[15:0]
        	Inst:	name[1:0]
        	Term:	D[7:0] (bound to 'D[7:0]')
        ModInstTerm:
        	Net:	c[15:0]
        	Inst:	order[1:0]
	Posit:	0 (bound to 'Q[7:0]')
        ModInstTerm:
        	Net:	d[15:0]
        	Inst:	order[1:0]
	Posit:	1 (bound to 'D[7:0]')
        ModInstTerm:
        	Net:	bx[7:0]
        	Inst:	order3[3:0]
	Posit:	1 (bound to 'out[1:0]')
        ModInstTerm:
        	Net:	bx[7:0]
        	Inst:	name3[3:0]
        	Term:	out[1:0] (bound to 'out[1:0]')
        ModInstTerm:
        	Net:	2*P
        	Inst:	name2[1:0]
        	Term:	clear (bound to 'clear')
        ModInstTerm:
        	Net:	2*P
        	Inst:	name[1:0]
        	Term:	clear (bound to 'clear')
        ModInstTerm:
        	Net:	2*Q
        	Inst:	name2[1:0]
        	Term:	clock (bound to 'clock')
        ModInstTerm:
        	Net:	2*Q
        	Inst:	name[1:0]
        	Term:	clock (bound to 'clock')
        ModInstTerm:
        	Net:	bx[7],bx[6],bx[5],bx[4],bx[3],bx[2],bx[1],bx[0],bx[7],bx[6],bx[5],bx[4],bx[3],bx[2],bx[1],bx[0]
        	Inst:	order2[1:0]
	Posit:	0 (bound to 'Q[7:0]')
        ModInstTerm:
        	Net:	bx[7],bx[6],bx[5],bx[4],bx[3],bx[2],bx[1],bx[0],bx[7],bx[6],bx[5],bx[4],bx[3],bx[2],bx[1],bx[0]
        	Inst:	name2[1:0]
        	Term:	Q[7:0] (bound to 'Q[7:0]')
        ModInstTerm:
        	Net:	by[7],by[6],by[5],by[4],by[3],by[2],by[1],by[0],by[7],by[6],by[5],by[4],by[3],by[2],by[1],by[0]
        	Inst:	order2[1:0]
	Posit:	1 (bound to 'D[7:0]')
        ModInstTerm:
        	Net:	by[7],by[6],by[5],by[4],by[3],by[2],by[1],by[0],by[7],by[6],by[5],by[4],by[3],by[2],by[1],by[0]
        	Inst:	name2[1:0]
        	Term:	D[7:0] (bound to 'D[7:0]')
        ModInstTerm:
        	Net:	2*X
        	Inst:	order2[1:0]
	Posit:	2 (bound to 'clear')
        ModInstTerm:
        	Net:	2*X
        	Inst:	order[1:0]