assignout.v

openaccess与verilog互相转化时所用的源代码

// Test the reader/writer ability to round-trip net assignments.

module assignTestSimple();
	wire a;
	wire b;

	assign a = b;
endmodule

module assignTestPort(input a);
	wire b;

	assign a = b;
endmodule


module assignTestBus(inout [7:0] a);
	wire [7:0] b;

	assign a = b;
endmodule


module assignTestBundle(input [1:0] a);
	wire b,c;

	assign a = {b,c};
	assign {b,c} = 2'b01;
endmodule


module assignTestRegister(in1, in2, in3, in4, in5, in6, out1, out2, out3);
    input           in1, in2;
    input   [1:0]   in3, in4;
    input   [2:0]   in5, in6;
    
    output          out1;
    output  [1:0]   out2;
    output  [2:0]   out3;
    
    reg             reg1;
    reg     [1:0]   reg2;
    reg     [2:0]   reg3;

    assign out1 = reg1;
    assign out2 = reg2;
    assign out3 = reg3;

endmodule



module assignTestLeaf(input in, output out);
    assign out = in;
endmodule


module assignTestOrder(input in1, in2, in3, output out1, out2, out3);
    wire in4;
    wire out4;
    
    // The order of input and output is deliberately inverted.
    assign in1 = out1;
    assign in2 = out2;
    assign in3 = out3;
    assign in4 = out4;
    
    assignTestLeaf  I1(in1, out1),
		    I2(out2, in2),
		    I3(in4, out4);
endmodule


module assignLong();
    wire    [127:0] x;
    wire    [63:0]  y;
    wire    [71:0]  z;
    
    assign x = 128'b10001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000;
    assign y = 'hfedcba9876543210;
    assign z = 'o765432107654321076543210;
endmodule

    
module top();
    assignTestSimple    I1();
    assignTestPort      I2();
    assignTestBus       I3();
    assignTestBundle    I4();
    assignTestRegister  I5();
    assignTestOrder	I6();
    assignLong		I7();
endmodule