ieeeports.v

openaccess与verilog互相转化时所用的源代码

module test(a,b,c,d,e,f,g,h,k);
       input  [7:0]  a;        // no explicit declaration - net is unsigned   
       input [7:0] b;   
       input signed [7:0] c;   
       input signed [7:0] d;  // no explicit net declaration - net is signed
       output  [7:0]  e;      // no explicit declaration - net is unsigned   
       output [7:0] f;   
       output signed [7:0] g;   
       output signed [7:0] h; // no explicit net declaration - net is signed
       inout [0] k;

       wire signed [7:0] b; // port b inherits signed attribute from net decl.
       wire [7:0] c;        // net c inherits signed attribute from port 
       reg signed [7:0] f;  // port f inherits signed attribute from reg decl. 
       reg [7:0] g;         // reg g inherits signed attribute from port
endmodule 


module same_port (.a(i), .b(i)); 
             // Name 'i' is declared inside the
             // module as a inout port. Names 'a' and 'b' are
             // defined for port connections.
        input i;
endmodule


module renamed_concat (.a({b,c}), f, .g(h[1]));  
          // Names 'b', 'c', 'f', 'h' are defined inside the module.
          // Names 'a', 'f', 'g' are defined for port connections.
          // Can use named port connections.
	input	b,c;
	input	f;
	output  [7:0] h;
endmodule

module split_ports (a[7:4], a[3:0]); 
                   // First port is upper 4 bits of 'a'.
                   // Second port is lower 4 bits of 'a'.
                   // Can't use named port connections because
                   // of part-select port 'a'.
	output [7:0] a;
endmodule


module overlapping (a[1:0], a[3:0]);
                   // First port is lower 2 bits of 'a'.
                   // Second port is all 4 bits of 'a'.
                   // Can't use named port connections because
                   // of part-select port 'a'.
    inout [3:0] a;
endmodule

module same_input (a,a,b,b,c[1],c[1],c[0],c[0]); 
          input         a;  // This is legal. The inputs are tied together. 
          output [1:0]  b;
          input [1:0]   c;
endmodule


module concat_ports ({c,d,g[1:0],h[0]}, .e(f)); 

          // Nets {c,d,g,h} receive the first
          // port bits. Name 'f' is declared inside the module.
          // Name 'e' is defined outside the module.
          // Can't use named port connections of first port.
          inout	c,d,f;
          inout [3:0] g;
          inout [1:0] h;
endmodule


module complex_ports(.a(b), .a(b), , .c(), f, .g(h), i[1]); 
    // This is legal IEEE 1364-2001 Verilog.
    // The first two terminals (labeled "a") are tied together on net "b"
    // The "a" terminals are "input" type terminals. 
    // After the first two terminals there is a deliberate gap.  This represents
    // an unnammed terminal with no connectivity.  It should have no effect other
    // than on the port order.
          input		b;
          input  [1:0]	f,h;
          output [1:1]	i;
endmodule


module unconnected_ports(.a(), .b(), .c());
endmodule


module bitMembers(a[0], b[1], c[2]);
    input   [0:1]	a;
    input   [0:1]	b;
    output  [0:3]	c;
endmodule


module busBundleMems(a[3:0], b[0], {a, b, c});
    input   [3:0]	a;
    input   [0:0]	b;
    input		c;
endmodule


		  
// Verify that mixing directions does not produce a warning as long as
// the bundle is not ported.
module fourBit(A);
    inout [3:0] A;
endmodule

module noWarning(input [1:0] in, output [1:0] out);
    fourBit I1(.A({in[0], in[1], out[0], out[1]}));
endmodule



module top();
    wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
    wire n1,n2,n3,n4;
    wire [1:0] n5,n6;

    complex_ports   i1(w1,w2,w3,w4,{w7,w8},{w9,w10},w11),
		    i2(.a(n1),.c(n2),.f(n5),.g(n6),.i(w11));
		  
    test            i3();
    same_port       i4();
    renamed_concat  i5();
    split_ports     i6();
    same_input      i7();
    concat_ports    i8();
    unconnected_ports i9();
    overlapping	    i10();
    bitMembers	    i11();
    busBundleMems   i12();

endmodule