pcr776966.v

openaccess与verilog互相转化时所用的源代码

// Verify forward reference handling when the order is not strictly
// top down or bottom up.  In this test, the module hierarchy 
// is 0, 1, 2, 3 but the order of module definition is 1, 2, 0 
// (3 is not defined).

module level1 ( QB,K,J,CLK,Q ); 

output   QB;
input   K;
input   J;
input   CLK;
output   Q;

level2  I8 ( .R( net6 ), .QB( net7 ), .S( net5 ), .Q( net8 ) );

endmodule

module level2 (R, S, QB, Q);
output Q;
output QB;
input R;
input S;

level3 I1 ( .Y( Q ), .B( QB ), .A( R ) );

endmodule


module level0 ( CP1,CP2,Q ); 

input   CP1;
input   CP2;
output [3:0]  Q;

level1 I9 ( .QB( net43 ), .K( POWR  ), .J( POWR  ), .CLK( net66 ), .Q( Q[0] ) );
 
endmodule