assign.v

openaccess与verilog互相转化时所用的源代码

module assignTestSimple();
	wire a;
	wire b;

	assign a = b;
endmodule

module assignTestPort(input a);
	wire b;

	assign a = b;
endmodule


module assignTestBus(inout [7:0] a);
	wire [7:0] b;

	assign a = b;
endmodule


module assignTestBundle(inout [1:0] a);
	wire b,c;

	assign a = {b,c};
	assign {b,c} = 2'b01;
endmodule


module assignTestRegister(in1, in2, in3, in4, in5, in6, out1, out2, out3);
    input           in1, in2;
    input   [1:0]   in3, in4;
    input   [2:0]   in5, in6;
    
    output          out1;
    output  [1:0]   out2;
    output  [2:0]   out3;
    
    reg             reg1;
    reg     [1:0]   reg2;
    reg     [2:0]   reg3;

    assign out1 = reg1;
    assign out2 = reg2;
    assign out3 = reg3;

endmodule


module assignConst();
    wire [1:0] n;
    
    assign n[0] = 1'b1;
    assign n[1] = 1'b0;
endmodule


module top();
    assignTestSimple    I1();
    assignTestPort      I2();
    assignTestBus       I3();
    assignTestBundle    I4();
    assignTestRegister  I5();
    assignConst		I6();
endmodule