ieeeportsout.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module overlapping (
    a[1:0],
    a);

    inout [3:0] a;

endmodule // overlapping


module unconnected_ports (
    .a(UNCONNECTED_oaVerilogIn0_),
    .b(UNCONNECTED_oaVerilogIn1_),
    .c(UNCONNECTED_oaVerilogIn2_));

    inout UNCONNECTED_oaVerilogIn0_;
    inout UNCONNECTED_oaVerilogIn1_;
    inout UNCONNECTED_oaVerilogIn2_;

endmodule // unconnected_ports


module concat_ports (
    {c,d,g[1],g[0],h[0]},
    .e(f));

    inout c;
    inout d;
    inout [3:0] g;
    inout [1:0] h;
    inout f;

endmodule // concat_ports


module same_input (
    a,
    ._oaVerilogIn1_a(a),
    b,
    ._oaVerilogIn1_b(b),
    c[1],
    c[1],
    c[0],
    c[0]);

    input a;
    output [1:0] b;
    input [1:0] c;

endmodule // same_input


module split_ports (
    a[7:4],
    a[3:0]);

    output [7:0] a;

endmodule // split_ports


module renamed_concat (
    .a({b,c}),
    f,
    .g(h[1]));

    input b;
    input c;
    input f;
    output [7:0] h;

endmodule // renamed_concat


module same_port (
    .a(i),
    .b(i));

    input i;

endmodule // same_port


module test (
    a,
    b,
    c,
    d,
    e,
    f,
    g,
    h,
    k);

    input [7:0] a;
    input [7:0] b;
    input [7:0] c;
    input [7:0] d;
    output [7:0] e;
    output [7:0] f;
    output [7:0] g;
    output [7:0] h;
    inout [0:0] k;

endmodule // test


module complex_ports (
    .a(b),
    ._oaVerilogIn1_a(b),
    UNCONNECTED_oaVerilogIn0_,
    .c(UNCONNECTED_oaVerilogIn1_),
    f,
    .g(h),
    i);

    input b;
    inout UNCONNECTED_oaVerilogIn0_;
    inout UNCONNECTED_oaVerilogIn1_;
    input [1:0] f;
    input [1:0] h;
    output [1:1] i;

endmodule // complex_ports


module top ();

    wire [1:0] n6;
    wire [1:0] n5;
    wire n4;
    wire n3;
    wire n2;
    wire n1;
    wire w11;
    wire w10;
    wire w9;
    wire w8;
    wire w7;
    wire w6;
    wire w5;
    wire w4;
    wire w3;
    wire w2;
    wire w1;

    overlapping i10 ();
    unconnected_ports i9 ();
    concat_ports i8 ();
    same_input i7 ();
    split_ports i6 ();
    renamed_concat i5 ();
    same_port i4 ();
    test i3 ();
    complex_ports i2 (
            .a(n1),
            .c(n2),
            .f(n5),
            .g(n6),
            .i(w11));
    complex_ports i1 (
            .a(w1),
            ._oaVerilogIn1_a(w2),
            .UNCONNECTED_oaVerilogIn0_(w3),
            .c(w4),
            .f({w7,w8}),
            .g({w9,w10}),
            .i(w11));
endmodule // top