external.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "fullAdder" view "netlist" 
// Language Version: 2001 

module halfAdder (
    carry,
    in1,
    in2,
    out);

    output carry;
    input [0:3] in1;
    input [0:3] in2;
    output [0:3] out;

endmodule // halfAdder


module or2 (
    in1,
    in2,
    out);

    input in1;
    input in2;
    output out;

endmodule // or2


module leaf (
    {a,b,c},
    {d,e},
    {f,g},
    in[0:1],
    in,
    out,
    w,
    x,
    y,
    z);

    inout a;
    inout b;
    inout c;
    inout d;
    inout e;
    inout f;
    inout g;
    input [0:3] in;
    output [0:3] out;
    inout [3:3] w;
    inout [2:2] x;
    inout [1:1] y;
    inout [0:0] z;

endmodule // leaf


module fullAdder (
    cin,
    cout,
    in1,
    in2,
    out);

    input cin;
    output cout;
    input [0:3] in1;
    input [0:3] in2;
    output [0:3] out;

    wire [0:3] sum;
    wire c1;
    wire c2;
    wire [0:3] x;
    wire zLow;
    wire zHigh;
    
    assign zLow = globals.LOW;
    assign zHigh = globals.HIGH;

    halfAdder I__0 (
            .carry(c1),
            .in1(in1),
            .in2(in2),
            .out(sum));
    halfAdder I__1 (
            .carry(c2),
            .in1(sum),
            .in2({3'b000,cin}),
            .out(out[0:3]));
    halfAdder extra (
            .in1({globals.LOW,globals.HIGH,globals.LOW,globals.HIGH}),
            .in2({globals.LOW,globals.LOW,globals.HIGH,globals.HIGH}),
            .out({out[0:1],x[0],x[0]}));
    or2 I__3 (
            .in1(c2),
            .in2(c1),
            .out(cout));
    leaf I__4 (
            x[0:1],
            x[0:3],
            {1'b0,cin,1'b0,cin});
endmodule // fullAdder