ieeeports.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
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Contents of IEEEports_design.test.netlist
    Contents of TOP module test
            Term: 'a[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'a[7:0]'
        	Position:	0
            Term: 'b[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'b[7:0]'
        	Position:	1
            Term: 'c[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'c[7:0]'
        	Position:	2
            Term: 'd[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'd[7:0]'
        	Position:	3
            Term: 'e[7:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	8
        	Net:		'e[7:0]'
        	Position:	4
            Term: 'f[7:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	8
        	Net:		'f[7:0]'
        	Position:	5
            Term: 'g[7:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	8
        	Net:		'g[7:0]'
        	Position:	6
            Term: 'h[7:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	8
        	Net:		'h[7:0]'
        	Position:	7
            Term: 'k[0]' (ModBusTermBit)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'k[0]'
        	Position:	8
            Net: 'a[7:0]' (ModBusNet)
            Net: 'b[7:0]' (ModBusNet)
            Net: 'c[7:0]' (ModBusNet)
            Net: 'd[7:0]' (ModBusNet)
            Net: 'e[7:0]' (ModBusNet)
            Net: 'f[7:0]' (ModBusNet)
            Net: 'g[7:0]' (ModBusNet)
            Net: 'h[7:0]' (ModBusNet)
            Net: 'k[0]' (ModBusNetBit)



Contents of IEEEports_design.same_port.netlist
    Contents of TOP module same_port
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'i'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'i'
        	Position:	1
            Net: 'i' (ModScalarNet)



Contents of IEEEports_design.renamed_concat.netlist
    Contents of TOP module renamed_concat
            Term: 'a[0:1]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'b,c'
        	Position:	0
            Term: 'f' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'f'
        	Position:	1
            Term: 'g' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'h[1]'
        	Position:	2
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'h[7:0]' (ModBusNet)
            Net: 'h[1]' (ModBusNetBit)
            Net: 'b,c' (ModBundleNet)



Contents of IEEEports_design.split_ports.netlist
    Contents of TOP module split_ports
            Term: 'a[7:4]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'a[7:4]'
        	Position:	0
            Term: 'a[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'a[3:0]'
        	Position:	1
            Net: 'a[7:0]' (ModBusNet)
            Net: 'a[7:4]' (ModBusNet)
            Net: 'a[3:0]' (ModBusNet)



Contents of IEEEports_design.overlapping.netlist
    Contents of TOP module overlapping
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Term: 'a[3:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	4
        	Net:		'a[3:0]'
        	Position:	1
            Net: 'a[3:0]' (ModBusNet)
            Net: 'a[1:0]' (ModBusNet)



Contents of IEEEports_design.same_input.netlist
    Contents of TOP module same_input
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: '_oaVerilogIn1_a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	1
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	2
            Term: '_oaVerilogIn1_b[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	3
            Term: 'c[1]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'c[1]'
        	Position:	4
            Term: '_oaVerilogIn1_c[1]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'c[1]'
        	Position:	5
            Term: 'c[0]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'c[0]'
        	Position:	6
            Term: '_oaVerilogIn1_c[0]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'c[0]'
        	Position:	7
            Net: 'a' (ModScalarNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c[1:0]' (ModBusNet)
            Net: 'c[1]' (ModBusNetBit)
            Net: 'c[0]' (ModBusNetBit)



Contents of IEEEports_design.concat_ports.netlist
    Contents of TOP module concat_ports
            Term: 'c,d,g[1],g[0],h[0]' (ModBundleTerm)
        	TermType:	inputOutput
        	NumBits:	5
        	Net:		'c,d,g[1],g[0],h[0]'
        	Position:	0
            Term: 'e' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'f'
        	Position:	1
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'g[3:0]' (ModBusNet)
            Net: 'h[1:0]' (ModBusNet)
            Net: 'h[0]' (ModBusNetBit)
            Net: 'c,d,g[1],g[0],h[0]' (ModBundleNet)
            Net: 'g[1:0]' (ModBusNet)



Contents of IEEEports_design.complex_ports.netlist
    Contents of TOP module complex_ports
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'b'
        	Position:	0
            Term: '_oaVerilogIn1_a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'UNCONNECTED_oaVerilogIn0_' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'UNCONNECTED_oaVerilogIn0_'
        	Position:	2
            Term: 'c' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'UNCONNECTED_oaVerilogIn1_'
        	Position:	3
            Term: 'f[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'f[1:0]'
        	Position:	4
            Term: 'g[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'h[1:0]'
        	Position:	5
            Term: 'i[1]' (ModBusTermBit)
        	TermType:	output
        	NumBits:	1
        	Net:		'i[1]'
        	Position:	6
            Net: 'b' (ModScalarNet)
            Net: 'f[1:0]' (ModBusNet)
            Net: 'h[1:0]' (ModBusNet)
            Net: 'i[1]' (ModBusNetBit)
            Net: 'UNCONNECTED_oaVerilogIn0_' (ModScalarNet)
            Net: 'UNCONNECTED_oaVerilogIn1_' (ModScalarNet)



Contents of IEEEports_design.unconnected_ports.netlist
    Contents of TOP module unconnected_ports
            Term: 'a' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'UNCONNECTED_oaVerilogIn0_'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'UNCONNECTED_oaVerilogIn1_'
        	Position:	1
            Term: 'c' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'UNCONNECTED_oaVerilogIn2_'
        	Position:	2
            Net: 'UNCONNECTED_oaVerilogIn0_' (ModScalarNet)
            Net: 'UNCONNECTED_oaVerilogIn1_' (ModScalarNet)
            Net: 'UNCONNECTED_oaVerilogIn2_' (ModScalarNet)



Contents of IEEEports_design.bitMembers.netlist
    Contents of TOP module bitMembers
            Term: 'a[0]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'a[0]'
        	Position:	0
            Term: 'b[1]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'b[1]'
        	Position:	1
            Term: 'c[2]' (ModBusTermBit)
        	TermType:	output
        	NumBits:	1
        	Net:		'c[2]'
        	Position:	2
            Net: 'a[0:1]' (ModBusNet)
            Net: 'a[0]' (ModBusNetBit)
            Net: 'b[0:1]' (ModBusNet)
            Net: 'b[1]' (ModBusNetBit)
            Net: 'c[0:3]' (ModBusNet)
            Net: 'c[2]' (ModBusNetBit)



Contents of IEEEports_design.busBundleMems.netlist
    Contents of TOP module busBundleMems
            Term: 'a[3:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	4
        	Net:		'a[3:0]'
        	Position:	0
            Term: 'b[0]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'b[0]'
        	Position:	1
            Term: 'a[3:0],b[0],c' (ModBundleTerm)
        	TermType:	input
        	NumBits:	6
        	Net:		'a[3:0],b[0],c'
        	Position:	2
            Net: 'a[3:0]' (ModBusNet)
            Net: 'b[0]' (ModBusNetBit)
            Net: 'c' (ModScalarNet)
            Net: 'a[3:0],b[0],c' (ModBundleNet)



Contents of IEEEports_design.fourBit.netlist
    Contents of TOP module fourBit
            Term: 'A[3:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	4
        	Net:		'A[3:0]'
        	Position:	0
            Net: 'A[3:0]' (ModBusNet)



Contents of IEEEports_design.noWarning.netlist
    Contents of TOP module noWarning
            Term: 'in[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'in[1:0]'
        	Position:	0
            Term: 'out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out[1:0]'
        	Position:	1
            Net: 'in[1:0]' (ModBusNet)
            Net: 'in[1]' (ModBusNetBit)
            Net: 'in[0]' (ModBusNetBit)
            Net: 'out[1:0]' (ModBusNet)
            Net: 'out[1]' (ModBusNetBit)
            Net: 'out[0]' (ModBusNetBit)
            Net: 'in[0],in[1],out[0],out[1]' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		IEEEports_design
        	CellName:		fourBit
        	ViewName:		netlist
        	Master Cell Name:	fourBit
        	NumBits:		1
        ModInstTerm:
        	Net:	in[0],in[1],out[0],out[1]
        	Inst:	I1
        	Term:	A[3:0] (bound to 'A[3:0]')



Contents of IEEEports_design.top.netlist
    Contents of TOP module top
            Net: 'w1' (ModScalarNet)
            Net: 'w2' (ModScalarNet)
            Net: 'w3' (ModScalarNet)
            Net: 'w4' (ModScalarNet)
            Net: 'w5' (ModScalarNet)
            Net: 'w6' (ModScalarNet)
            Net: 'w7' (ModScalarNet)
            Net: 'w8' (ModScalarNet)
            Net: 'w9' (ModScalarNet)
            Net: 'w10' (ModScalarNet)
            Net: 'w11' (ModScalarNet)
            Net: 'n1' (ModScalarNet)
            Net: 'n2' (ModScalarNet)
            Net: 'n3' (ModScalarNet)
            Net: 'n4' (ModScalarNet)
            Net: 'n5[1:0]' (ModBusNet)
            Net: 'n6[1:0]' (ModBusNet)
            Net: 'w7,w8' (ModBundleNet)
            Net: 'w9,w10' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		i1
        	LibName:		IEEEports_design
        	CellName:		complex_ports
        	ViewName:		netlist
        	Master Cell Name:	complex_ports
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i2
        	LibName:		IEEEports_design
        	CellName:		complex_ports
        	ViewName:		netlist
        	Master Cell Name:	complex_ports
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i3
        	LibName:		IEEEports_design
        	CellName:		test
        	ViewName:		netlist
        	Master Cell Name:	test
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i4
        	LibName:		IEEEports_design
        	CellName:		same_port
        	ViewName:		netlist
        	Master Cell Name:	same_port
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i5
        	LibName:		IEEEports_design
        	CellName:		renamed_concat
        	ViewName:		netlist
        	Master Cell Name:	renamed_concat
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i6
        	LibName:		IEEEports_design
        	CellName:		split_ports
        	ViewName:		netlist
        	Master Cell Name:	split_ports
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i7
        	LibName:		IEEEports_design
        	CellName:		same_input
        	ViewName:		netlist
        	Master Cell Name:	same_input
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i8
        	LibName:		IEEEports_design
        	CellName:		concat_ports
        	ViewName:		netlist
        	Master Cell Name:	concat_ports
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i9
        	LibName:		IEEEports_design
        	CellName:		unconnected_ports
        	ViewName:		netlist
        	Master Cell Name:	unconnected_ports
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i10
        	LibName:		IEEEports_design
        	CellName:		overlapping
        	ViewName:		netlist
        	Master Cell Name:	overlapping
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		i11
        	LibName:		IEEEports_design
        	CellName:		bitMembers
        	ViewName:		netlist
        	Master Cell Name:	bitMembers
        	NumBits:		1
        ModInst:
        	Is Bound:		yes