hierout.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module level1 (
    l1_in,
    l1_out);

    input [7:0] l1_in;
    output l1_out;

endmodule // level1


module level2B (
    l2B_in,
    l2B_out);

    input l2B_in;
    output [1:0] l2B_out;

    wire [7:0] l2B_busReg;

    level1 I1 (
            .l1_in(l2B_busReg),
            .l1_out(l2B_out[1]));
endmodule // level2B


module level2A (
    l2A_in,
    l2A_out);

    input l2A_in;
    output l2A_out;

    wire [7:0] l2A_busReg;

    level1 I1 (
            .l1_in(l2A_busReg),
            .l1_out(l2A_out));
endmodule // level2A


module level3 (
    l3_in,
    l3_out);

    input l3_in;
    output [1:0] l3_out;


    level2B I2B (
            .l2B_in(l3_in),
            .l2B_out(l3_out));
    level2A I1A (
            .l2A_in(l3_in),
            .l2A_out(l3_out[1]));
endmodule // level3


module top ();

    wire [1:0] bus3;
    wire [1:0] bus2;
    wire [1:0] bus1;
    wire scalar3;
    wire scalar2;
    wire scalar1;

    level3 I3 (
            .l3_in(scalar3),
            .l3_out(bus3));
    level3 I2 (
            .l3_in(scalar2),
            .l3_out(bus2));
    level3 I1 (
            .l3_in(scalar1),
            .l3_out(bus1));
endmodule // top