termnotfoundleaf1.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 15 行

// Test the reader's ability to detect an extra terminal in the leaf cell's
// declaration when using ANSI style port declarations.



module scalarLeaf(input in, output out, inout aux);
endmodule



module top1();
    scalarLeaf  I1(a, b, c);
endmodule