implicitwire.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Warning: Always blocks are not implemented
Contents of implicitWire_design.NAND.netlist
    Contents of TOP module NAND
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	0
            Term: 'in1' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in1'
        	Position:	1
            Term: 'in2' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in2'
        	Position:	2
            Net: 'out' (ModScalarNet)
            Net: 'in1' (ModScalarNet)
            Net: 'in2' (ModScalarNet)



Contents of implicitWire_design.top.netlist
    Contents of TOP module top
            Term: 'sum' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'sum'
        	Position:	0
            Term: 'aIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'aIn'
        	Position:	1
            Term: 'bIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'bIn'
        	Position:	2
            Term: 'cIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'cIn'
        	Position:	3
            Net: 'sum' (ModScalarNet)
            Net: 'aIn' (ModScalarNet)
            Net: 'bIn' (ModScalarNet)
            Net: 'cIn' (ModScalarNet)
            Net: 'x2' (ModScalarNet)
            Net: 'cOut' (ModScalarNet)
            Net: 'x8' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		implicitWire_design
        	CellName:		NAND
        	ViewName:		netlist
        	Master Cell Name:	NAND
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	LibName:		implicitWire_design
        	CellName:		NAND
        	ViewName:		netlist
        	Master Cell Name:	NAND
        	NumBits:		1
        ModInstTerm:
        	Net:	aIn
        	Inst:	I1
	Posit:	1 (bound to 'in1')
        ModInstTerm:
        	Net:	bIn
        	Inst:	I1
	Posit:	2 (bound to 'in2')
        ModInstTerm:
        	Net:	x2
        	Inst:	I2
	Posit:	1 (bound to 'in1')
        ModInstTerm:
        	Net:	x2
        	Inst:	I1
	Posit:	0 (bound to 'out')
        ModInstTerm:
        	Net:	cOut
        	Inst:	I2
	Posit:	0 (bound to 'out')
        ModInstTerm:
        	Net:	x8
        	Inst:	I2
	Posit:	2 (bound to 'in2')



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Warning: Always blocks are not implemented
Info: The top module is top
Contents of implicitWire_designEMH.top.netlist
    Contents of module NAND
            Term: 'in2' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in2'
        	Position:	2
            Term: 'in1' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in1'
        	Position:	1
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	0
            Net: 'in2' (ModScalarNet)
            Net: 'in1' (ModScalarNet)
            Net: 'out' (ModScalarNet)
    Contents of TOP module top
            Term: 'cIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'cIn'
        	Position:	3
            Term: 'bIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'bIn'
        	Position:	2
            Term: 'aIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'aIn'
        	Position:	1
            Term: 'sum' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'sum'
        	Position:	0
            Net: 'x8' (ModScalarNet)
            Net: 'cOut' (ModScalarNet)
            Net: 'x2' (ModScalarNet)
            Net: 'cIn' (ModScalarNet)
            Net: 'bIn' (ModScalarNet)
            Net: 'aIn' (ModScalarNet)
            Net: 'sum' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	Master Cell Name:	NAND
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	NAND
        	NumBits:		1
        ModInstTerm:
        	Net:	x8
        	Inst:	I2
	Posit:	2 (bound to 'in2')
        ModInstTerm:
        	Net:	cOut
        	Inst:	I2
	Posit:	0 (bound to 'out')
        ModInstTerm:
        	Net:	x2
        	Inst:	I2
	Posit:	1 (bound to 'in1')
        ModInstTerm:
        	Net:	x2
        	Inst:	I1
	Posit:	0 (bound to 'out')
        ModInstTerm:
        	Net:	bIn
        	Inst:	I1
	Posit:	2 (bound to 'in2')
        ModInstTerm:
        	Net:	aIn
        	Inst:	I1
	Posit:	1 (bound to 'in1')



Reader succeeded