assignout.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module assignLong ();

    wire [71:0] z;
    wire [63:0] y;
    wire [127:0] x;
    
    assign z = 72'b111110101100011010001000111110101100011010001000111110101100011010001000;
    assign y = 64'b1111111011011100101110101001100001110110010101000011001000010000;
    assign x = 128'b10001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000;
endmodule // assignLong


module assignTestLeaf (
    in,
    out);

    input in;
    output out;

    
    assign out = in;
endmodule // assignTestLeaf


module assignTestOrder (
    in1,
    in2,
    in3,
    out1,
    out2,
    out3);

    input in1;
    input in2;
    input in3;
    output out1;
    output out2;
    output out3;

    wire out4;
    wire in4;
    
    assign out4 = in4;
    assign out3 = in3;
    assign out2 = in2;
    assign out1 = in1;

    assignTestLeaf I3 (
            .in(in4),
            .out(out4));
    assignTestLeaf I2 (
            .in(out2),
            .out(in2));
    assignTestLeaf I1 (
            .in(in1),
            .out(out1));
endmodule // assignTestOrder


module assignTestRegister (
    in1,
    in2,
    in3,
    in4,
    in5,
    in6,
    out1,
    out2,
    out3);

    input in1;
    input in2;
    input [1:0] in3;
    input [1:0] in4;
    input [2:0] in5;
    input [2:0] in6;
    output out1;
    output [1:0] out2;
    output [2:0] out3;

    wire [2:0] reg3;
    wire [1:0] reg2;
    wire reg1;
    
    assign out3[0] = reg3[0];
    assign out3[1] = reg3[1];
    assign out3[2] = reg3[2];
    assign out2[0] = reg2[0];
    assign out2[1] = reg2[1];
    assign out1 = reg1;
endmodule // assignTestRegister


module assignTestBundle (
    a);

    input [1:0] a;

    wire c;
    wire b;
    
    assign a[0] = c;
    assign c = 1'b1;
    assign a[1] = b;
    assign b = 1'b0;
endmodule // assignTestBundle


module assignTestBus (
    a);

    inout [7:0] a;

    wire [7:0] b;
    
    assign a[0] = b[0];
    assign a[1] = b[1];
    assign a[2] = b[2];
    assign a[3] = b[3];
    assign a[4] = b[4];
    assign a[5] = b[5];
    assign a[6] = b[6];
    assign a[7] = b[7];
endmodule // assignTestBus


module assignTestPort (
    a);

    input a;

    wire b;
    
    assign b = a;
endmodule // assignTestPort


module assignTestSimple ();

    wire b;
    wire a;
    
    assign a = b;
endmodule // assignTestSimple


module top ();

    assignLong I7 ();
    assignTestOrder I6 ();
    assignTestRegister I5 ();
    assignTestBundle I4 ();
    assignTestBus I3 ();
    assignTestPort I2 ();
    assignTestSimple I1 ();
endmodule // top