outoptions.v

openaccess与verilog互相转化时所用的源代码

// Test the writer's ability to handle leaf cells.



module top();
    wire        a, b;
    
    leaf1   I4(a, b);
    leaf2   I5(a, b);
endmodule



module leaf1(input in, output out);
endmodule



module leaf2(.in(x), .out(y));
    input   in;
    output  out;
    wire    x, y;
endmodule