width.v

openaccess与verilog互相转化时所用的源代码

// This test verifies that the translator can handle connecting a narrow
// net to a wide terminal.

module D8BB(in, out);
	input	[7:0]	in;
	output 		out;
endmodule

module A8BB(in, out);
	input	[0:7]	in;
	output 		out;
endmodule

module top();
	wire	[3:0]	a;
	wire		b,c,d,e;
	wire		x,y;
	wire	[15:0]	z;
	wire	[31:0]	p;
	
	// In the following cases, the module is defined before it is
	// instantiated.
	D8BB	I01(.in(a), .out(x));
	D8BB	I02(.in({b,c,d,e}), .out(y));
	D8BB	I21(.in(z), .out(x));
	D8BB	I22(.in({b,c,c,c,c,c,c,c,c,c,c,c,c,c,c,d}), .out(x));
	D8BB	I03(a, x);
	D8BB	I04({b,c,d,e}, y);
	D8BB	I23(z, x);
	D8BB	I24({b,c,c,c,c,c,c,c,c,c,c,c,c,c,c,d}, x);

	A8BB	I05(.in(a), .out(x));
	A8BB	I06(.in({b,c,d,e}), .out(y));
	A8BB	I25(.in(z), .out(x));
	A8BB	I26(.in({b,c,c,c,c,c,c,c,c,c,c,c,c,c,c,d}), .out(x));
	A8BB	I07(a, x);
	A8BB	I08({b,c,d,e}, y);
	A8BB	I27(z, x);
	A8BB	I28({b,c,c,c,c,c,c,c,c,c,c,c,c,c,c,d}, x);

	// In the following cases, the module is instantiated before it is
	// defined.	
	D16BB	I09(.in(a), .out(x));
	D16BB	I10(.in({b,c,d,e}), .out(y));
	D16BB	I29(.in(p), .out(x));
	D16BB	I30(.in({b,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,d}), .out(x));
	D16BB	I11(a, x);
	D16BB	I12({b,c,d,e}, y);

	A16BB	I13(.in(a), .out(x));
	A16BB	I14(.in({b,c,d,e}), .out(y));
	A16BB	I15(a, x);
	A16BB	I16({b,c,d,e}, y);


	// In these cases, the module is defined before it is instantiated,
	// but the number of bits connected to the terminal is different than
	// the number of bits previously connected to the same terminal. 
	D8BB	I17({b,c,c,c,c,c,d}, y);
	A8BB	I18(.in({b,c,c,c,c,c,d}), .out(x));

	// In these cases, the module is instantiated before it is defined,
	// but the number of bits connected to the terminal is different than
	// the number of bits previously connected to the same terminal. 
	D16BB	I19({b,c,c,c,c,c,c,c,c,c,c,c,c,c,d}, y);
	A16BB	I20(.in({b,c,c,c,c,c,c,c,c,c,c,c,c,c,d}), .out(x));
endmodule

module D16BB(in, out);
	input	[15:0]	in;
	output 		out;
endmodule

module A16BB(in, out);
	input	[0:15]	in;
	output 		out;
endmodule