pcr739428.v

openaccess与verilog互相转化时所用的源代码

// Verify that the ported nets (not the port aliases) are declared
// input/output/inout.

module leaf (.a(x), .b(y), .c({w, z[3], z[2], z[1]}));
	inout		w;
	input		x;
	output	[3:0]	y;
	inout 	[7:0]	z;
endmodule

module top();
	wire		p;
	wire	[3:0]	q;
	wire	[3:0]	r;

	leaf	I1(.a(p), .b(q), .c(r));
endmodule