annotate.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* Annotate
******************************************************************************
Warning: (./annotate.v: 19): The direction of terminal "inconsistent" is not declared consistently
Contents of annotateLibB.noDirection.right
    Contents of TOP module noDirection
            Term: 'in[0]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'in[0]'
            Term: 'in[1]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'in[1]'
            Term: 'out[0:1]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out[0:1]'
            Term: 'inconsistent' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'inconsistent'
        	Position:	3
            Term: 'in[0:1]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'in[0:1]'
        	Position:	0
            Term: 'out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out[1:0]'
        	Position:	1
            Term: 'extra[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'extra[1:0]'
        	Position:	2
            Net: 'in[0]' (ModBusNetBit)
            Net: 'in[1]' (ModBusNetBit)
            Net: 'out[0:1]' (ModBusNet)
            Net: 'inconsistent' (ModScalarNet)
            Net: 'in[0:1]' (ModBusNet)
            Net: 'out[1:0]' (ModBusNet)
            Net: 'extra[1:0]' (ModBusNet)



Contents of annotateLibA.noOrderHasTop.right
    Contents of TOP module noOrderHasTop
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'aux' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'aux'
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)
            Net: 'aux' (ModScalarNet)



Info: The top module is hasOrderNoTop
Contents of annotateLibA.hasOrderNoTop.right
    Contents of TOP module hasOrderNoTop
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	1
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	0
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)



Info: The top module is noOrderNoTop
Contents of annotateLibB.noOrderNoTop.right
    Contents of TOP module noOrderNoTop
            Term: 'in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'in'
        	Position:	0
            Term: 'out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'out'
        	Position:	1
            Term: 'aux' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'aux'
            Net: 'in' (ModScalarNet)
            Net: 'out' (ModScalarNet)
            Net: 'aux' (ModScalarNet)



Warning: Cell "extra" was not found in any library
Warning: (./annotate.v: 64): The direction of terminal "a[0:1]" is not declared consistently
Warning: (./annotate.v: 65): The direction of terminal "b[0:3]" is not declared consistently
Warning: (./annotate.v: 66): The direction of terminal "{c,d}" is not declared consistently
Contents of annotateLibB.bitMember.right
    Contents of TOP module bitMember
            Term: 'a[0:1]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'a[0:1]'
            Term: 'a[0]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'a[0]'
        	Position:	0
            Term: 'b[0:3]' (ModBusTerm)
        	TermType:	input
        	NumBits:	4
        	Net:		'b[0:3]'
            Term: 'b[1]' (ModBusTermBit)
        	TermType:	input
        	NumBits:	1
        	Net:		'b[1]'
        	Position:	1
            Term: 'c,d' (ModBundleTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'c,d'
            Term: 'c' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Term: 'e[0]' (ModBusTermBit)
        	TermType:	output
        	NumBits:	1
        	Net:		'e[0]'
        	Position:	3
            Net: 'a[0:1]' (ModBusNet)
            Net: 'a[0]' (ModBusNetBit)
            Net: 'b[0:3]' (ModBusNet)
            Net: 'b[1]' (ModBusNetBit)
            Net: 'c,d' (ModBundleNet)
            Net: 'c' (ModScalarNet)
            Net: 'e[0]' (ModBusNetBit)



Warning: Verilog module "inconsistentTop" is represented by the top module of annotateLibB.inconsistentTop.right, "unexpectedTop"
Warning: (./annotate.v: 75): The direction of terminal "a" is not declared consistently
Contents of annotateLibB.inconsistentTop.right
    Contents of TOP module unexpectedTop
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Net: 'a' (ModScalarNet)



Contents of annotateLibB.noModules.right
    Contents of TOP module noModules
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Net: 'a' (ModScalarNet)



Annotater succeeded



******************************************************************************
Dumping contents of library annotateLibA
******************************************************************************
// Verilog file for cell "noOrderHasTop" view "wrong" 
// Language Version: 2001 

module noOrderHasTop (
    aux,
    in,
    out);

    inout aux;
    input in;
    output out;

endmodule // noOrderHasTop


// Verilog file for cell "noOrderHasTop" view "right" 
// Language Version: 2001 

module noOrderHasTop (
    in,
    out);

    input in;
    output out;

    wire aux;
endmodule // noOrderHasTop


// Verilog file for cell "hasOrderNoTop" view "wrong" 
// Language Version: 2001 

module hasOrderNoTop (
    in,
    out);

    input in;
    output out;

endmodule // hasOrderNoTop


// Verilog file for cell "hasOrderNoTop" view "right" 
// Language Version: 2001 

module hasOrderNoTop (
    out,
    in);

    output out;
    input in;

endmodule // hasOrderNoTop


******************************************************************************
Dumping contents of library annotateLibB
******************************************************************************
Design annotateLibB.noOrderNoTop.wrong does not have a top module
// Verilog file for cell "noOrderNoTop" view "right" 
// Language Version: 2001 

module noOrderNoTop (
    in,
    out);

    input in;
    output out;

    wire aux;
endmodule // noOrderNoTop


// Verilog file for cell "noDirection" view "right" 
// Language Version: 2001 

module noDirection (
    in,
    out,
    extra,
    inconsistent);

    input [0:1] in;
    output [1:0] out;
    output [1:0] extra;
    output inconsistent;

endmodule // noDirection


// Verilog file for cell "bitMember" view "right" 
// Language Version: 2001 

module bitMember (
    a[0],
    b[1],
    c,
    e);

    input [0:1] a;
    input [0:3] b;
    output c;
    output [0:0] e;

endmodule // bitMember


// Verilog file for cell "inconsistentTop" view "right" 
// Language Version: 2001 

module unexpectedTop (
    a);

    input a;

endmodule // unexpectedTop


// Verilog file for cell "noModules" view "right" 
// Language Version: 2001 

module noModules (
    a);

    input a;

endmodule // noModules