gaps.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of gaps_design.bottom.netlist
    Contents of TOP module bottom
            Term: 'a' (ModScalarTerm)
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        	Net:		'a'
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            Term: 'b[1:0]' (ModBusTerm)
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            Term: 'UNCONNECTED_oaVerilogIn0_' (ModScalarTerm)
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            Net: 'a' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c,d' (ModBundleNet)
            Net: 'UNCONNECTED_oaVerilogIn0_' (ModScalarNet)



Contents of gaps_design.mid.netlist
    Contents of TOP module mid
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	inputOutput
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        	Net:		'a[1:0]'
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            Term: 'b[1:0]' (ModBusTerm)
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            Term: 'c' (ModScalarTerm)
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        	Net:		'c'
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            Net: 'a[1:0]' (ModBusNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c' (ModScalarNet)



Contents of gaps_design.top.netlist
    Contents of TOP module top
            Net: 'A[1:0]' (ModBusNet)
            Net: 'K[1:0]' (ModBusNet)
            Net: 'P[1:0]' (ModBusNet)
            Net: 'T[1:0]' (ModBusNet)
            Net: 'B[1:0]' (ModBusNet)
            Net: 'F[1:0]' (ModBusNet)
            Net: 'Q[1:0]' (ModBusNet)
            Net: 'U[1:0]' (ModBusNet)
            Net: 'C' (ModScalarNet)
            Net: 'D' (ModScalarNet)
            Net: 'E' (ModScalarNet)
            Net: 'G' (ModScalarNet)
            Net: 'H' (ModScalarNet)
            Net: 'J' (ModScalarNet)
            Net: 'L' (ModScalarNet)
            Net: 'M' (ModScalarNet)
            Net: 'N' (ModScalarNet)
            Net: 'R' (ModScalarNet)
            Net: 'S' (ModScalarNet)
            Net: 'V' (ModScalarNet)
            Net: 'W' (ModScalarNet)
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        	Inst:	I3
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        ModInstTerm:
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        	Inst:	I4
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        ModInstTerm:
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        	Inst:	I4
	Posit:	4 (bound to 'f')
        ModInstTerm:
        	Net:	S
        	Inst:	I5
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        	Net:	V
        	Inst:	I5
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Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Info: The top module is top
Contents of gaps_designEMH.top.netlist
    Contents of module bottom
            Term: 'f' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'f'
        	Position:	4
            Term: 'UNCONNECTED_oaVerilogIn0_' (ModScalarTerm)
        	TermType:	inputOutput
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        	Net:		'UNCONNECTED_oaVerilogIn0_'
        	Position:	3
            Term: 'c,d' (ModBundleTerm)
        	TermType:	inputOutput
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        	Net:		'c,d'
        	Position:	2
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	inputOutput
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        	Net:		'b[1:0]'
        	Position:	1
            Term: 'a' (ModScalarTerm)
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        	Net:		'a'
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            Net: 'UNCONNECTED_oaVerilogIn0_' (ModScalarNet)
            Net: 'c,d' (ModBundleNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'f' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'a' (ModScalarNet)
    Contents of module mid
            Term: 'c' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Term: 'b[1:0]' (ModBusTerm)
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            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Net: 'c' (ModScalarNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'a[1:0]' (ModBusNet)
    Contents of TOP module top
            Net: 'W' (ModScalarNet)
            Net: 'V' (ModScalarNet)
            Net: 'S' (ModScalarNet)
            Net: 'R' (ModScalarNet)
            Net: 'N' (ModScalarNet)
            Net: 'M' (ModScalarNet)
            Net: 'L' (ModScalarNet)
            Net: 'J' (ModScalarNet)
            Net: 'H' (ModScalarNet)
            Net: 'G' (ModScalarNet)
            Net: 'E' (ModScalarNet)
            Net: 'D' (ModScalarNet)
            Net: 'C' (ModScalarNet)
            Net: 'U[1:0]' (ModBusNet)
            Net: 'Q[1:0]' (ModBusNet)
            Net: 'F[1:0]' (ModBusNet)
            Net: 'B[1:0]' (ModBusNet)
            Net: 'T[1:0]' (ModBusNet)
            Net: 'P[1:0]' (ModBusNet)
            Net: 'K[1:0]' (ModBusNet)
            Net: 'A[1:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
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        	Master Cell Name:	mid
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I5
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        ModInst:
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        	Master Cell Name:	bottom
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        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	Master Cell Name:	bottom
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        ModInst:
        	Is Bound:		yes
        	InstName:		I2
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        ModInstTerm:
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        ModInstTerm:
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        	Inst:	I4
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        ModInstTerm:
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        	Inst:	I4
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        	Net:	M
        	Inst:	I3
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        	Net:	L
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        	Inst:	I2
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        ModInstTerm:
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        	Inst:	I2
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        	Net:	D
        	Inst:	I1
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        	Net:	C
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        	Net:	B[1:0]
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Reader succeeded