annotate.v

openaccess与verilog互相转化时所用的源代码

// This is the input file for the "annotate" test.  This tests the
// annotation utility's ability to assign terminal positions and to
// detect the top module of designs in a set of leaf libraries.
// In all cases the there are two Views of each leaf: "right" and "wrong"
// Only the "right" leaf should be selected for modification.  The "wrong"
// leaf should remain untouched.

// This module contains bus terminals that do not have bit order.  Also
// the terminals do not have position and the second port's bit order is 
// changed. The inconsistent port is created with "inout" direction but is 
// declared "output" (the translator should produce a warning and change the 
// direction to match the Verilog). The "extra" port is a multi-bit port and
// does not appear in the original design. The body of the module should be 
// ignored.
module noDirection(
    input   [0:1]   in,
    output  [1:0]   out,
    output  [1:0]   extra,
    output	    inconsistent);
    
    wire	    ignoreThis;
    wire	    ignoreThisToo = 1'b1, ignoreThisAlso = 1'b0;
    wire    [0:1]   ignoreThisBus;
    
    assign	    ignoreThis = ignoreThisBus[0];
    
    ingnore inst2Bignored(ingoreThis, ignoreThisToo);
endmodule


// This module has a top module but there is no order on the 
// terminals.  Additionally, there is a third terminal in the
// module that is not specified in the Verilog.  The third terminal
// should be ignored and no error should be generated.
module noOrderHasTop(in, out);
endmodule



// This module has order but no top module.  The top module should
// be detected and the order of the terminals will be reset to the
// order of the terminals in this module declaration.  Again there
// is a third terminal that will remain untouched by the annotation.
module hasOrderNoTop(out, in);
endmodule



// This module has no order and no top module. Otherwise it is 
// identical to the other two modules.
module noOrderNoTop(in, out);
endmodule



// This module does not correspond to any module in any leaf library.
module extra(in, out);
endmodule



// This module ports only single bit members of busTerms.
module bitMember(a[0], b[1], c, e);
    input   [0:1]	a;
    input   [0:3]	b;
    output		c;
    output  [0:0]	e;
endmodule



// The design that is associated with this module has a top module with an
// unexpected name.
module inconsistentTop(a);
    input a;
endmodule



// The design associated with this Verilog module has no modules at all.
module noModules(a);
    input a;
endmodule