stub.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of stub_design.empty.netlist
    Contents of TOP module empty
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	1
            Term: 'c' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Net: 'a' (ModScalarNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c' (ModScalarNet)



Contents of stub_design.top.netlist
    Contents of TOP module top
            Net: 'wireToA' (ModScalarNet)
            Net: 'wireToC' (ModScalarNet)
            Net: 'wireToX' (ModScalarNet)
            Net: 'wireToZ' (ModScalarNet)
            Net: 'busToB[1:0]' (ModBusNet)
            Net: 'busToY[1:0]' (ModBusNet)
            Net: 'wideBusToB[3:0]' (ModBusNet)
            Net: 'wideBusToY[3:0]' (ModBusNet)
            Net: '2*wireToZ' (ModBundleNet)
            Net: '2*wireToX' (ModBundleNet)
            Net: '2*wireToA' (ModBundleNet)
            Net: '2*wireToC' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		designInst
        	LibName:		stub_design
        	CellName:		empty
        	ViewName:		netlist
        	Master Cell Name:	empty
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		lowNames
        	LibName:		stub_design
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		highNames
        	LibName:		stub_design
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		vectorInst[1:0]
        	LibName:		stub_design
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		2
        ModInst:
        	Is Bound:		no
        	InstName:		scalarOrder
        	LibName:		stub_design
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		vectorOrder[1:0]
        	LibName:		stub_design
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		2
        ModInstTerm:
        	Net:	wireToA
        	Inst:	scalarOrder
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	wireToA
        	Inst:	lowNames
        	Term:	a (not bound)
        ModInstTerm:
        	Net:	wireToA
        	Inst:	designInst
        	Term:	a (bound to 'a')
        ModInstTerm:
        	Net:	wireToC
        	Inst:	scalarOrder
	Posit:	2 (not bound)
        ModInstTerm:
        	Net:	wireToC
        	Inst:	lowNames
        	Term:	c (not bound)
        ModInstTerm:
        	Net:	wireToC
        	Inst:	designInst
        	Term:	c (bound to 'c')
        ModInstTerm:
        	Net:	wireToX
        	Inst:	scalarOrder
	Posit:	3 (not bound)
        ModInstTerm:
        	Net:	wireToX
        	Inst:	highNames
        	Term:	x (not bound)
        ModInstTerm:
        	Net:	wireToZ
        	Inst:	scalarOrder
	Posit:	5 (not bound)
        ModInstTerm:
        	Net:	wireToZ
        	Inst:	highNames
        	Term:	z (not bound)
        ModInstTerm:
        	Net:	busToB[1:0]
        	Inst:	scalarOrder
	Posit:	1 (not bound)
        ModInstTerm:
        	Net:	busToB[1:0]
        	Inst:	lowNames
        	Term:	b[1:0] (not bound)
        ModInstTerm:
        	Net:	busToB[1:0]
        	Inst:	designInst
        	Term:	b[1:0] (bound to 'b[1:0]')
        ModInstTerm:
        	Net:	busToY[1:0]
        	Inst:	scalarOrder
	Posit:	4 (not bound)
        ModInstTerm:
        	Net:	busToY[1:0]
        	Inst:	highNames
        	Term:	y[1:0] (not bound)
        ModInstTerm:
        	Net:	wideBusToB[3:0]
        	Inst:	vectorOrder[1:0]
	Posit:	1 (not bound)
        ModInstTerm:
        	Net:	wideBusToY[3:0]
        	Inst:	vectorOrder[1:0]
	Posit:	4 (not bound)
        ModInstTerm:
        	Net:	wideBusToY[3:0]
        	Inst:	vectorInst[1:0]
        	Term:	y[1:0] (not bound)
        ModInstTerm:
        	Net:	2*wireToZ
        	Inst:	vectorOrder[1:0]
	Posit:	5 (not bound)
        ModInstTerm:
        	Net:	2*wireToZ
        	Inst:	vectorInst[1:0]
        	Term:	z (not bound)
        ModInstTerm:
        	Net:	2*wireToX
        	Inst:	vectorOrder[1:0]
	Posit:	3 (not bound)
        ModInstTerm:
        	Net:	2*wireToX
        	Inst:	vectorInst[1:0]
        	Term:	x (not bound)
        ModInstTerm:
        	Net:	2*wireToA
        	Inst:	vectorOrder[1:0]
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	2*wireToC
        	Inst:	vectorOrder[1:0]
	Posit:	2 (not bound)



Warning: Unresolved references exist for the following modules: 
	stub

Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Contents of stub_designEMH.empty.abstract
    Contents of TOP module empty
            Term: 'c' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	1
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Net: 'c' (ModScalarNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'a' (ModScalarNet)



Info: The top module is top
Warning: Unresolved references exist for the following modules: 
	stub

Contents of stub_designEMH.top.netlist
    Contents of TOP module top
            Net: '2*wireToC' (ModBundleNet)
            Net: '2*wireToA' (ModBundleNet)
            Net: '2*wireToX' (ModBundleNet)
            Net: '2*wireToZ' (ModBundleNet)
            Net: 'wideBusToY[3:0]' (ModBusNet)
            Net: 'wideBusToB[3:0]' (ModBusNet)
            Net: 'busToY[1:0]' (ModBusNet)
            Net: 'busToB[1:0]' (ModBusNet)
            Net: 'wireToZ' (ModScalarNet)
            Net: 'wireToX' (ModScalarNet)
            Net: 'wireToC' (ModScalarNet)
            Net: 'wireToA' (ModScalarNet)
        ModInst:
        	Is Bound:		no
        	InstName:		vectorOrder[1:0]
        	LibName:		stub_designEMH
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		2
        ModInst:
        	Is Bound:		no
        	InstName:		scalarOrder
        	LibName:		stub_designEMH
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		vectorInst[1:0]
        	LibName:		stub_designEMH
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		2
        ModInst:
        	Is Bound:		no
        	InstName:		highNames
        	LibName:		stub_designEMH
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		no
        	InstName:		lowNames
        	LibName:		stub_designEMH
        	CellName:		stub
        	ViewName:		abstract
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		designInst
        	LibName:		stub_designEMH
        	CellName:		empty
        	ViewName:		abstract
        	Master Cell Name:	empty
        	NumBits:		1
        ModInstTerm:
        	Net:	2*wireToC
        	Inst:	vectorOrder[1:0]
	Posit:	2 (not bound)
        ModInstTerm:
        	Net:	2*wireToA
        	Inst:	vectorOrder[1:0]
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	2*wireToX
        	Inst:	vectorOrder[1:0]
	Posit:	3 (not bound)
        ModInstTerm:
        	Net:	2*wireToX
        	Inst:	vectorInst[1:0]
        	Term:	x (not bound)
        ModInstTerm:
        	Net:	2*wireToZ
        	Inst:	vectorOrder[1:0]
	Posit:	5 (not bound)
        ModInstTerm:
        	Net:	2*wireToZ
        	Inst:	vectorInst[1:0]
        	Term:	z (not bound)
        ModInstTerm:
        	Net:	wideBusToY[3:0]
        	Inst:	vectorOrder[1:0]
	Posit:	4 (not bound)
        ModInstTerm:
        	Net:	wideBusToY[3:0]
        	Inst:	vectorInst[1:0]
        	Term:	y[1:0] (not bound)
        ModInstTerm:
        	Net:	wideBusToB[3:0]
        	Inst:	vectorOrder[1:0]
	Posit:	1 (not bound)
        ModInstTerm:
        	Net:	busToY[1:0]
        	Inst:	scalarOrder
	Posit:	4 (not bound)
        ModInstTerm:
        	Net:	busToY[1:0]
        	Inst:	highNames
        	Term:	y[1:0] (not bound)
        ModInstTerm:
        	Net:	busToB[1:0]
        	Inst:	scalarOrder
	Posit:	1 (not bound)
        ModInstTerm:
        	Net:	busToB[1:0]
        	Inst:	lowNames
        	Term:	b[1:0] (not bound)
        ModInstTerm:
        	Net:	busToB[1:0]
        	Inst:	designInst
        	Term:	b[1:0] (bound to 'b[1:0]')
        ModInstTerm:
        	Net:	wireToZ
        	Inst:	scalarOrder
	Posit:	5 (not bound)
        ModInstTerm:
        	Net:	wireToZ
        	Inst:	highNames
        	Term:	z (not bound)
        ModInstTerm:
        	Net:	wireToX
        	Inst:	scalarOrder
	Posit:	3 (not bound)
        ModInstTerm:
        	Net:	wireToX
        	Inst:	highNames
        	Term:	x (not bound)
        ModInstTerm:
        	Net:	wireToC
        	Inst:	scalarOrder
	Posit:	2 (not bound)
        ModInstTerm:
        	Net:	wireToC
        	Inst:	lowNames
        	Term:	c (not bound)
        ModInstTerm:
        	Net:	wireToC
        	Inst:	designInst
        	Term:	c (bound to 'c')
        ModInstTerm:
        	Net:	wireToA
        	Inst:	scalarOrder
	Posit:	0 (not bound)
        ModInstTerm:
        	Net:	wireToA
        	Inst:	lowNames
        	Term:	a (not bound)
        ModInstTerm:
        	Net:	wireToA
        	Inst:	designInst
        	Term:	a (bound to 'a')



Reader succeeded