bundle.v

openaccess与verilog互相转化时所用的源代码

// Test reader/writer roundtrip of bundles.

module bundlePort({q[1:0],ckout,q[6]}, out, other[0], other[3:2]);
	input	[7:0]	q;
	input		ckout;
	output 		out;
	inout	[3:0]	other;
endmodule

module bunLevel1(l1_in, l1_out);
    input  [7:0]    l1_in;
    output	    l1_out;
endmodule


module widePorts(input [127:0] in1, input [63:0] in2, input [71:0] in3,
		 output out);
endmodule


module top(input [3:0] topIn, output [3:0] topOut);
    wire [2:0]	busInA;
    wire [3:0]	busInB;
    wire	wireIn;
    wire [3:3]	busOut;
    wire	x,y,z;

    bunLevel1 I1 (.l1_in({busInA, wireIn, busInB}),
                  .l1_out(busOut)),
              I2 (.l1_in({'b000, wireIn, 'b1111}),
                  .l1_out(wireOut)),
              I3 (.l1_in({busInA, wireIn, 'b1111}),
                  .l1_out(wireOut));
                  
                  
    widePorts I4 (128'b10001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000,
		  'hfedcba9876543210, 'o765432107654321076543210, wireIn);
		  
    bundlePort I5 (busInB, busOut, x, {y,z});
    
    bunLevel1 I6 (.l1_in({\foo[0] , \foo[1] , \foo[2] , \foo[3] , \foo[4] , 
			  \foo[5] , \foo[6] , \foo[7] }),
		  .l1_out(wireOut)), 
	      I7 (.l1_in({\foo[0] , \foo[0] , \foo[0] , \foo[0] , \foo[0] , 
			  \foo[0] , \foo[0] ,                     \foo[0] }),
		  .l1_out(wireOut));
		  
    // Combine a ported bus with a wire in a concatenation.
    bunLevel1 I8 (.l1_in({topIn[0], topIn[1], topIn[2], topIn[3], 
                          busInB[0], busInB[1], busInB[2], busInB[3]}),
		  .l1_out(wireIn));
endmodule