param.v

openaccess与verilog互相转化时所用的源代码

module xorx
	#(parameter width=3, delay=10)
	(out,in1,in2);
	output [width:0] out;
	input  [width:0] in1,in2;
	
	assign #(delay) out = xin1^xin2;
endmodule


module top(output [3:0] a1,a2);
 	reg [3:0] b1,c1,b2,c2;
 	
 	xorx #(4,0) a(a1,b1,c1),
	            b(a2,b2,c2);
endmodule