connect.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of connect_design.scalarLeaf.netlist
    Contents of TOP module scalarLeaf
            Term: 'scalarIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'scalarIn'
        	Position:	0
            Term: 'scalarOut' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'scalarOut'
        	Position:	1
            Net: 'scalarIn' (ModScalarNet)
            Net: 'scalarOut' (ModScalarNet)



Contents of connect_design.twoBusLeaf.netlist
    Contents of TOP module twoBusLeaf
            Term: 'busIn[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'busIn[1:0]'
        	Position:	0
            Term: 'busOut[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'busOut[1:0]'
        	Position:	1
            Net: 'busIn[1:0]' (ModBusNet)
            Net: 'busOut[1:0]' (ModBusNet)



Contents of connect_design.scalarAndBusLeaf.netlist
    Contents of TOP module scalarAndBusLeaf
            Term: 'scalarIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'scalarIn'
        	Position:	0
            Term: 'busOut[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'busOut[1:0]'
        	Position:	1
            Net: 'scalarIn' (ModScalarNet)
            Net: 'busOut[1:0]' (ModBusNet)



Contents of connect_design.top.netlist
    Contents of TOP module top
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'e[1:0]' (ModBusNet)
            Net: 'e[1]' (ModBusNetBit)
            Net: 'e[0]' (ModBusNetBit)
            Net: 'f[1:0]' (ModBusNet)
            Net: 'f[1]' (ModBusNetBit)
            Net: 'f[0]' (ModBusNetBit)
            Net: 'a,b' (ModBundleNet)
            Net: 'c,d' (ModBundleNet)
            Net: 'b,c' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		s0
        	LibName:		connect_design
        	CellName:		scalarLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s1
        	LibName:		connect_design
        	CellName:		scalarLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s2
        	LibName:		connect_design
        	CellName:		scalarLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s3
        	LibName:		connect_design
        	CellName:		scalarLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		tb1
        	LibName:		connect_design
        	CellName:		twoBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	twoBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		tb2
        	LibName:		connect_design
        	CellName:		twoBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	twoBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		tb3
        	LibName:		connect_design
        	CellName:		twoBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	twoBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb0
        	LibName:		connect_design
        	CellName:		scalarAndBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb1
        	LibName:		connect_design
        	CellName:		scalarAndBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb2
        	LibName:		connect_design
        	CellName:		scalarAndBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb3
        	LibName:		connect_design
        	CellName:		scalarAndBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb5
        	LibName:		connect_design
        	CellName:		scalarAndBusLeaf
        	ViewName:		netlist
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInstTerm:
        	Net:	a
        	Inst:	sb5
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	a
        	Inst:	s2
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	a
        	Inst:	s0
	Posit:	1 (bound to 'scalarOut')
        ModInstTerm:
        	Net:	b
        	Inst:	sb1
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	b
        	Inst:	sb0
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	b
        	Inst:	s2
        	Term:	scalarOut (bound to 'scalarOut')
        ModInstTerm:
        	Net:	b
        	Inst:	s0
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	sb1
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	sb0
	Posit:	1 (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	tb3
        	Term:	busIn[1:0] (bound to 'busIn[1:0]')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	tb2
	Posit:	0 (bound to 'busIn[1:0]')
        ModInstTerm:
        	Net:	e[1]
        	Inst:	s1
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[0]
        	Inst:	sb3
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[0]
        	Inst:	sb2
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[0]
        	Inst:	s3
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	sb3
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	sb2
	Posit:	1 (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	tb3
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	tb2
	Posit:	1 (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1]
        	Inst:	s3
        	Term:	scalarOut (bound to 'scalarOut')
        ModInstTerm:
        	Net:	f[0]
        	Inst:	s1
	Posit:	1 (bound to 'scalarOut')
        ModInstTerm:
        	Net:	a,b
        	Inst:	tb1
        	Term:	busIn[1:0] (bound to 'busIn[1:0]')
        ModInstTerm:
        	Net:	c,d
        	Inst:	tb1
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	b,c
        	Inst:	sb5
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Info: The top module is top
Contents of connect_designEMH.top.netlist
    Contents of module scalarLeaf
            Term: 'scalarOut' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'scalarOut'
        	Position:	1
            Term: 'scalarIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'scalarIn'
        	Position:	0
            Net: 'scalarOut' (ModScalarNet)
            Net: 'scalarIn' (ModScalarNet)
    Contents of module twoBusLeaf
            Term: 'busOut[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'busOut[1:0]'
        	Position:	1
            Term: 'busIn[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'busIn[1:0]'
        	Position:	0
            Net: 'busOut[1:0]' (ModBusNet)
            Net: 'busIn[1:0]' (ModBusNet)
    Contents of module scalarAndBusLeaf
            Term: 'busOut[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'busOut[1:0]'
        	Position:	1
            Term: 'scalarIn' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'scalarIn'
        	Position:	0
            Net: 'busOut[1:0]' (ModBusNet)
            Net: 'scalarIn' (ModScalarNet)
    Contents of TOP module top
            Net: 'b,c' (ModBundleNet)
            Net: 'c,d' (ModBundleNet)
            Net: 'a,b' (ModBundleNet)
            Net: 'f[0]' (ModBusNetBit)
            Net: 'f[1]' (ModBusNetBit)
            Net: 'f[1:0]' (ModBusNet)
            Net: 'e[0]' (ModBusNetBit)
            Net: 'e[1]' (ModBusNetBit)
            Net: 'e[1:0]' (ModBusNet)
            Net: 'd' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'a' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		sb5
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb3
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb2
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb1
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		sb0
        	Master Cell Name:	scalarAndBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		tb3
        	Master Cell Name:	twoBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		tb2
        	Master Cell Name:	twoBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		tb1
        	Master Cell Name:	twoBusLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s3
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s2
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s1
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		s0
        	Master Cell Name:	scalarLeaf
        	NumBits:		1
        ModInstTerm:
        	Net:	b,c
        	Inst:	sb5
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	c,d
        	Inst:	tb1
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	a,b
        	Inst:	tb1
        	Term:	busIn[1:0] (bound to 'busIn[1:0]')
        ModInstTerm:
        	Net:	f[0]
        	Inst:	s1
	Posit:	1 (bound to 'scalarOut')
        ModInstTerm:
        	Net:	f[1]
        	Inst:	s3
        	Term:	scalarOut (bound to 'scalarOut')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	sb3
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	sb2
	Posit:	1 (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	tb3
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	f[1:0]
        	Inst:	tb2
	Posit:	1 (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	e[0]
        	Inst:	sb3
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[0]
        	Inst:	sb2
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[0]
        	Inst:	s3
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[1]
        	Inst:	s1
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	sb1
        	Term:	busOut[1:0] (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	sb0
	Posit:	1 (bound to 'busOut[1:0]')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	tb3
        	Term:	busIn[1:0] (bound to 'busIn[1:0]')
        ModInstTerm:
        	Net:	e[1:0]
        	Inst:	tb2
	Posit:	0 (bound to 'busIn[1:0]')
        ModInstTerm:
        	Net:	b
        	Inst:	sb1
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	b
        	Inst:	sb0
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	b
        	Inst:	s2
        	Term:	scalarOut (bound to 'scalarOut')
        ModInstTerm:
        	Net:	b
        	Inst:	s0
	Posit:	0 (bound to 'scalarIn')
        ModInstTerm:
        	Net:	a
        	Inst:	sb5
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	a
        	Inst:	s2
        	Term:	scalarIn (bound to 'scalarIn')
        ModInstTerm:
        	Net:	a
        	Inst:	s0
	Posit:	1 (bound to 'scalarOut')



Reader succeeded