portdecls.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Warning: Always blocks are not implemented
Contents of portDecls_design.simpleScalar.netlist
    Contents of TOP module simpleScalar
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'c' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.simpleBus.netlist
    Contents of TOP module simpleBus
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	1
            Term: 'c[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'c[1:0]'
        	Position:	2
            Net: 'a[1:0]' (ModBusNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c[1:0]' (ModBusNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.simpleANSIscalar.netlist
    Contents of TOP module simpleANSIscalar
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'c' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.simpleANSIbus.netlist
    Contents of TOP module simpleANSIbus
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	1
            Term: 'c[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'c[1:0]'
        	Position:	2
            Net: 'a[1:0]' (ModBusNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c[1:0]' (ModBusNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.scalar.netlist
    Contents of TOP module scalar
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'c' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Term: 'd' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'd'
        	Position:	3
            Term: 'e' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'e'
        	Position:	4
            Term: 'f' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'f'
        	Position:	5
            Term: 'g' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'g'
        	Position:	6
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'e' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'g' (ModScalarNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.bus.netlist
    Contents of TOP module bus
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	1
            Term: 'c[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'c[1:0]'
        	Position:	2
            Term: 'd[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'd[1:0]'
        	Position:	3
            Term: 'e[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'e[1:0]'
        	Position:	4
            Term: 'f[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'f[1:0]'
        	Position:	5
            Term: 'g[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'g[1:0]'
        	Position:	6
            Net: 'a[1:0]' (ModBusNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c[1:0]' (ModBusNet)
            Net: 'd[1:0]' (ModBusNet)
            Net: 'e[1:0]' (ModBusNet)
            Net: 'f[1:0]' (ModBusNet)
            Net: 'g[1:0]' (ModBusNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.ANSIscalar.netlist
    Contents of TOP module ANSIscalar
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'c' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'c'
        	Position:	2
            Term: 'd' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'd'
        	Position:	3
            Term: 'e' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'e'
        	Position:	4
            Term: 'f' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'f'
        	Position:	5
            Term: 'g' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'g'
        	Position:	6
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c' (ModScalarNet)
            Net: 'd' (ModScalarNet)
            Net: 'e' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'g' (ModScalarNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.ANSIbus.netlist
    Contents of TOP module ANSIbus
            Term: 'a[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'a[1:0]'
        	Position:	0
            Term: 'b[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'b[1:0]'
        	Position:	1
            Term: 'c[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'c[1:0]'
        	Position:	2
            Term: 'd[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'd[1:0]'
        	Position:	3
            Term: 'e[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'e[1:0]'
        	Position:	4
            Term: 'f[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'f[1:0]'
        	Position:	5
            Term: 'g[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'g[1:0]'
        	Position:	6
            Net: 'a[1:0]' (ModBusNet)
            Net: 'b[1:0]' (ModBusNet)
            Net: 'c[1:0]' (ModBusNet)
            Net: 'd[1:0]' (ModBusNet)
            Net: 'e[1:0]' (ModBusNet)
            Net: 'f[1:0]' (ModBusNet)
            Net: 'g[1:0]' (ModBusNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.mixed.netlist
    Contents of TOP module mixed
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'c[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'c[1:0]'
        	Position:	2
            Term: 'd[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'd[1:0]'
        	Position:	3
            Term: 'e' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'e'
        	Position:	4
            Term: 'f' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'f'
        	Position:	5
            Term: 'g[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'g[1:0]'
        	Position:	6
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c[1:0]' (ModBusNet)
            Net: 'd[1:0]' (ModBusNet)
            Net: 'e' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'g[1:0]' (ModBusNet)
            Net: 'h[1:0]' (ModBusNet)
            Net: 'i' (ModScalarNet)
            Net: 'j' (ModScalarNet)
            Net: 'k[1:0]' (ModBusNet)
            Net: 'l[1:0]' (ModBusNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.ANSImixed.netlist
    Contents of TOP module ANSImixed
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Term: 'b' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'b'
        	Position:	1
            Term: 'c[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'c[1:0]'
        	Position:	2
            Term: 'd[1:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	2
        	Net:		'd[1:0]'
        	Position:	3
            Term: 'e' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'e'
        	Position:	4
            Term: 'f' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'f'
        	Position:	5
            Term: 'g[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'g[1:0]'
        	Position:	6
            Term: 'h[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'h[1:0]'
        	Position:	7
            Term: 'i' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'i'
        	Position:	8
            Term: 'j' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'j'
        	Position:	9
            Term: 'k[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'k[1:0]'
        	Position:	10
            Term: 'l[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'l[1:0]'
        	Position:	11
            Net: 'a' (ModScalarNet)
            Net: 'b' (ModScalarNet)
            Net: 'c[1:0]' (ModBusNet)
            Net: 'd[1:0]' (ModBusNet)
            Net: 'e' (ModScalarNet)
            Net: 'f' (ModScalarNet)
            Net: 'g[1:0]' (ModBusNet)
            Net: 'h[1:0]' (ModBusNet)
            Net: 'i' (ModScalarNet)
            Net: 'j' (ModScalarNet)
            Net: 'k[1:0]' (ModBusNet)
            Net: 'l[1:0]' (ModBusNet)



Warning: Always blocks are not implemented
Contents of portDecls_design.resize.netlist
    Contents of TOP module resize
            Term: 'clk' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'clk'
        	Position:	0
            Term: 'out1[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out1[1:0]'
        	Position:	1
            Term: 'out2[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out2[1:0]'
        	Position:	2
            Term: 'out3[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out3[1:0]'
        	Position:	3
            Term: 'out4[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'out4[1:0]'
        	Position:	4
            Term: 'out5[3:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	4
        	Net:		'out5[3:0]'
        	Position:	5
            Net: 'clk' (ModScalarNet)
            Net: 'out1[1:0]' (ModBusNet)
            Net: 'out2[1:0]' (ModBusNet)
            Net: 'out3[1:0]' (ModBusNet)
            Net: 'out4[1:0]' (ModBusNet)
            Net: 'out5[3:0]' (ModBusNet)



Contents of portDecls_design.top.netlist
    Contents of TOP module top
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		portDecls_design
        	CellName:		simpleScalar
        	ViewName:		netlist
        	Master Cell Name:	simpleScalar
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	LibName:		portDecls_design
        	CellName:		simpleBus
        	ViewName:		netlist
        	Master Cell Name:	simpleBus
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	LibName:		portDecls_design
        	CellName:		simpleANSIscalar
        	ViewName:		netlist
        	Master Cell Name:	simpleANSIscalar
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I4
        	LibName:		portDecls_design
        	CellName:		simpleANSIbus
        	ViewName:		netlist
        	Master Cell Name:	simpleANSIbus
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I5
        	LibName:		portDecls_design
        	CellName:		scalar
        	ViewName:		netlist
        	Master Cell Name:	scalar
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I6
        	LibName:		portDecls_design
        	CellName:		bus
        	ViewName:		netlist
        	Master Cell Name:	bus
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I7
        	LibName:		portDecls_design
        	CellName:		ANSIscalar
        	ViewName:		netlist
        	Master Cell Name:	ANSIscalar
        	NumBits:		1
        ModInst:
        	Is Bound:		yes