datatype.v

openaccess与verilog互相转化时所用的源代码

// Verify that we can handle the datatypes:
//   wire, tri*, wand, wor, supply*

module scalar(input in, output out);
	always @(in);
endmodule

module wireTest();
	wire wire_a,wire_b;
	wand wand_a,wand_b;
	wor  wor_a,wor_b;

	scalar order_wire(wire_a,wire_b),
	       named_wire(.in(wire_a),.out(wire_b)),
	       order_wand(wand_a,wand_b),
	       named_wand(.in(wand_a),.out(wand_b)),
	       order_wor(wor_a,wor_b),
	       named_wor(.in(wor_a),.out(wor_b));

endmodule

module triTest();
	tri     tri_a,tri_b;
	triand  triand_a,triand_b;
	trior   trior_a,trior_b;
	tri0    tri0_a,tri0_b;
	tri1    tri1_a,tri1_b;

	scalar order_tri(tri_a,tri_b),
	       named_tri(.in(tri_a),.out(tri_b)),
	       order_triand(triand_a,triand_b),
	       named_triand(.in(triand_a),.out(triand_b)),
	       order_trior(trior_a,trior_b),
	       named_trior(.in(trior_a),.out(trior_b)),
	       order_tri0(tri0_a,tri0_b),
	       named_tri0(.in(tri0_a),.out(tri0_b)),
	       order_tri1(tri1_a,tri1_b),
	       named_tri1(.in(tri1_a),.out(tri1_b));

endmodule

module supplyTest();
	supply0 gnd;
	supply1 vdd;

	scalar order_supply(vdd,gnd),
	       named_supply(.in(vdd),.out(gnd));

endmodule

module top();
    wireTest    I1();
    triTest     I2();
    supplyTest  I3();
endmodule