portdecls.v

openaccess与verilog互相转化时所用的源代码

// Port declarations test
//
// Verify that we can handle the port declaration tokens:
// input, output and inout
// and that we can handle the "traditional" as well as ANSI port
// declaration formats.

module simpleScalar(a,b,c);
	input  a;
	output b;
	inout  c;

	always @(a);
endmodule


module simpleBus(a,b,c);
	input  [1:0] a;
	output [1:0] b;
	inout  [1:0] c;

	always @(a);
endmodule


module simpleANSIscalar(
	input  a,
	output b,
	inout  c);

	always @(a);
endmodule


module simpleANSIbus(
	input  [1:0] a,
	output [1:0] b,
	inout  [1:0] c);

	always @(a);
endmodule

module scalar(a,b,c,d,e,f,g);
	input  a,b,c;
	output d,e;
	inout  f,g;

	always @(a);
endmodule


module bus(a,b,c,d,e,f,g);
	input  [1:0] a,b,c;
	output [1:0] d,e;
	inout  [1:0] f,g;

	always @(a);
endmodule

module ANSIscalar(
	input  a,b,c,
	output d,e,
	inout  f,g);

	always @(a);
endmodule


module ANSIbus(
	input  [1:0] a,b,c,
	output [1:0] d,e,
	inout  [1:0] f,g);

	always @(a);
endmodule


module mixed(a,b,c,d,e,f,g);
	input        a,b;
	input  [1:0] c,d;
	output       e,f;
	output [1:0] g,h;
	inout        i,j;
	inout  [1:0] k,l;

	always @(a);
endmodule


module ANSImixed(
	input        a,b,
	input  [1:0] c,d,
	output       e,f,
	output [1:0] g,h,
	inout        i,j,
	inout  [1:0] k,l);

	always @(a);
endmodule


// In the "resize" test, ports are declared using scalar names
// that represent register busses. The scalar nets produced
// by the input and output declarations should be replaced by
// bus nets in the reg declarations.
module resize(clk, out1, out2, out3, out4, out5);
    input clk;
    output out1,out2,out3,out4,out5;
    reg [1:0] out1,out2,out3,out4;
    reg [3:0] out5;

    always @(posedge clk);
endmodule


module top();
    simpleScalar        I1();
    simpleBus           I2();
    simpleANSIscalar    I3();
    simpleANSIbus       I4();
    scalar              I5();
    bus                 I6();
    ANSIscalar          I7();
    ANSIbus             I8();
    mixed               I9();
    ANSImixed           I10();
    resize              I11();
endmodule