bundle.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module bundlePort (
    {q[1],q[0],ckout,q[6]},
    out,
    other[0],
    other[3:2]);

    input [7:0] q;
    input ckout;
    output out;
    inout [3:0] other;

endmodule // bundlePort


module widePorts (
    in1,
    in2,
    in3,
    out);

    input [127:0] in1;
    input [63:0] in2;
    input [71:0] in3;
    output out;

endmodule // widePorts


module bunLevel1 (
    l1_in,
    l1_out);

    input [7:0] l1_in;
    output l1_out;

endmodule // bunLevel1


module top (
    topIn,
    topOut);

    input [3:0] topIn;
    output [3:0] topOut;

    wire \foo[7] ;
    wire \foo[6] ;
    wire \foo[5] ;
    wire \foo[4] ;
    wire \foo[3] ;
    wire \foo[2] ;
    wire \foo[1] ;
    wire \foo[0] ;
    wire wireOut;
    wire z;
    wire y;
    wire x;
    wire [3:3] busOut;
    wire wireIn;
    wire [3:0] busInB;
    wire [2:0] busInA;

    bunLevel1 I8 (
            .l1_in({topIn[0],topIn[1],topIn[2],topIn[3],busInB[0],busInB[1],busInB[2],busInB[3]}),
            .l1_out(wireIn));
    bunLevel1 I7 (
            .l1_in({\foo[0] ,\foo[0] ,\foo[0] ,\foo[0] ,\foo[0] ,\foo[0] ,\foo[0] ,\foo[0] }),
            .l1_out(wireOut));
    bunLevel1 I6 (
            .l1_in({\foo[0] ,\foo[1] ,\foo[2] ,\foo[3] ,\foo[4] ,\foo[5] ,\foo[6] ,\foo[7] }),
            .l1_out(wireOut));
    bundlePort I5 (
            busInB,
            busOut,
            x,
            {y,z});
    widePorts I4 (
            .in1(128'b10001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001000),
            .in2(64'b1111111011011100101110101001100001110110010101000011001000010000),
            .in3(72'b111110101100011010001000111110101100011010001000111110101100011010001000),
            .out(wireIn));
    bunLevel1 I3 (
            .l1_in({busInA,wireIn,4'b1111}),
            .l1_out(wireOut));
    bunLevel1 I2 (
            .l1_in({3'b000,wireIn,4'b1111}),
            .l1_out(wireOut));
    bunLevel1 I1 (
            .l1_in({busInA,wireIn,busInB}),
            .l1_out(busOut));
endmodule // top