nonstruct.v

openaccess与verilog互相转化时所用的源代码

// This test case is intended to test the reader's ability to parse (and ignore) 
// non-structural syntax such as "case" and "function" statements.  For the 
// purposes of this test, simply parsing the Verilog without generating any 
// syntax errors is considered "success".



`timescale 1ns/1ps



config cfg;
    design mylib.mycell;
endconfig



module gen #(parameter width = 3, base = 10, delay = 10)
           (out, in1, in2);
     
     localparam signed [0:1]    a=1.0, b=2.0;
     parameter  signed [0:1]    c=3.0, d=4.0;      
           
     output [0  +: width] out;
     input  [2  -: width] in1, in2;
     wire   [base +: width] x;
     wire   [base -: width] y;
     wire   [base : width]  z;
     
     generate
        genvar i;
        for (i = 1; i <= width; i = i + 1)
        begin: doit
            assign #delay
                out[i] = in1[i] & in2[i];
        end
     endgenerate
endmodule



module pCell #(parameter real width = 1.0; parameter integer base = 2; parameter time delay = 10;)
           (output out, input in1, input in2);
endmodule



module child(a, y , powr, grnd) ;
    (* powerSensitivity = "powr", groundSensitivity = "grnd" *)
    input a;
    
    (* powerSensitivity = "powr", groundSensitivity = "grnd" *)
    output y;
    
    (* netExpr = "vdd(my_globals.\\vdd! )" *) inout powr;
    (* netExpr = "gnd(my_globals.\\gnd! )" *) inout grnd;
    (* netExpr = "clock(my_globals.\\clck! )" *) wire CK;
endmodule



module top(input [31:0] in, output [31:0] out);
    parameter                   tClock  = 20, 
                                p0      = 'd0, 
                                p1      = 'h1, 
                                p2      = 'o2, 
                                p3      = 'b11;
                               
    localparam integer          xParam  = 0;
    localparam real             piParam = 3.14159;
    localparam time             tParam  = $time;
    localparam realtime         rtParam = $time;
    
    time                        t;
    realtime                    rt;
    real                        pi = 3.14159, rho, sigma;                  
                       
    integer                     int;         
    integer [15:0]              intarray;
    reg                         go;
    
    reg     [15:0]  signed      m[0:8191];
    reg             signed      n[1];
    reg     [12:0]  signed	pc;
    reg     [12:0]  signed 	acc;
    reg     [15:0]        	ir;
    reg		  	        ck;
    
    reg     signed  [12:0]      mcnd;
    wire    signed  [12:0]      prod;
    wire                        done = 0;
    
    (* netSet = "vdd, vss" *)
    (* vdd = "DVDD" , vss = "DVSS" *) child
    I1 ( w, x, y, z );
    
    gen I2();
    
    initial
      begin
        $readmemh("memory.data", m);
        ck = 0;
        $monitor("clock = %d at time %d", ck, $time);
        acc <= top.multiply(2, 3);
      end

    always
      begin
        #tClock ck = !ck;
        
        @(posedge ck)
            begin: block
                event eve;
                ir <= m[pc];
                int = in + 1;
                ->eve;
            end
        @(posedge ck)
            case(ir[15:13])
                p0:     pc <= m[ir[12:0]];
                p1:     pc <= pc+m[ir[12:0]];
                p2:     acc <= -m[ir[12:0]];
                p3:     m[ir[12:0]] <= acc;
                3'b100,
                3'b101: acc <= acc - m[ir[12:0]];
                3'b110: pc <= acc < 0 ? pc + 0:1:2 : 0;
                3'b111: begin
                            wait(~done) mcnd <= m[ir[12:0]];
                            go <= 1;
                            wait(done);
                            acc <= multiply(acc, m[ir[12:0]]);
                        end
            endcase
        pc <= pc + 1;
     end
     
     function signed [12:0] multiply
        (input  signed  [12:0]  a,
         input  signed  [15:0]  b);
         
         begin: serialMult
            reg [5:0]   mcnd, mpy;
            mpy = b[5:0];
            mcnd = a[5:0];
            multiply = 0;
            repeat(6)
                begin
                    if (mpy[0])
                        multiply = multiply + {mcnd, 6'b000000};
                    multiply = multiply >> 1;
                    mpy = mpy >> 1;
                end
            begin: break
                for (i = 0; i < n; i = i + 1)
                    begin: continue
                        if (a == 0) 
                            disable continue;
                        if (a == b) 
                            disable break;
                    end
            end
         end
     endfunction      
endmodule