hier.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of hier_design.level1.netlist
    Contents of TOP module level1
            Term: 'l1_in[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'l1_in[7:0]'
        	Position:	0
            Term: 'l1_out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'l1_out'
        	Position:	1
            Net: 'l1_in[7:0]' (ModBusNet)
            Net: 'l1_out' (ModScalarNet)



Contents of hier_design.level2A.netlist
    Contents of TOP module level2A
            Term: 'l2A_in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'l2A_in'
        	Position:	0
            Term: 'l2A_out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'l2A_out'
        	Position:	1
            Net: 'l2A_in' (ModScalarNet)
            Net: 'l2A_out' (ModScalarNet)
            Net: 'l2A_busReg[7:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		hier_design
        	CellName:		level1
        	ViewName:		netlist
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	l2A_out
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
        ModInstTerm:
        	Net:	l2A_busReg[7:0]
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[7:0]')



Contents of hier_design.level2B.netlist
    Contents of TOP module level2B
            Term: 'l2B_in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'l2B_in'
        	Position:	0
            Term: 'l2B_out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'l2B_out[1:0]'
        	Position:	1
            Net: 'l2B_in' (ModScalarNet)
            Net: 'l2B_out[1:0]' (ModBusNet)
            Net: 'l2B_out[1]' (ModBusNetBit)
            Net: 'l2B_busReg[7:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		hier_design
        	CellName:		level1
        	ViewName:		netlist
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	l2B_out[1]
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
        ModInstTerm:
        	Net:	l2B_busReg[7:0]
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[7:0]')



Contents of hier_design.level3.netlist
    Contents of TOP module level3
            Term: 'l3_in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'l3_in'
        	Position:	0
            Term: 'l3_out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'l3_out[1:0]'
        	Position:	1
            Net: 'l3_in' (ModScalarNet)
            Net: 'l3_out[1:0]' (ModBusNet)
            Net: 'l3_out[1]' (ModBusNetBit)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1A
        	LibName:		hier_design
        	CellName:		level2A
        	ViewName:		netlist
        	Master Cell Name:	level2A
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2B
        	LibName:		hier_design
        	CellName:		level2B
        	ViewName:		netlist
        	Master Cell Name:	level2B
        	NumBits:		1
        ModInstTerm:
        	Net:	l3_in
        	Inst:	I2B
	Posit:	0 (bound to 'l2B_in')
        ModInstTerm:
        	Net:	l3_in
        	Inst:	I1A
	Posit:	0 (bound to 'l2A_in')
        ModInstTerm:
        	Net:	l3_out[1:0]
        	Inst:	I2B
	Posit:	1 (bound to 'l2B_out[1:0]')
        ModInstTerm:
        	Net:	l3_out[1]
        	Inst:	I1A
	Posit:	1 (bound to 'l2A_out')



Contents of hier_design.top.netlist
    Contents of TOP module top
            Net: 'scalar1' (ModScalarNet)
            Net: 'scalar2' (ModScalarNet)
            Net: 'scalar3' (ModScalarNet)
            Net: 'bus1[1:0]' (ModBusNet)
            Net: 'bus2[1:0]' (ModBusNet)
            Net: 'bus3[1:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	LibName:		hier_design
        	CellName:		level3
        	ViewName:		netlist
        	Master Cell Name:	level3
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	LibName:		hier_design
        	CellName:		level3
        	ViewName:		netlist
        	Master Cell Name:	level3
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	LibName:		hier_design
        	CellName:		level3
        	ViewName:		netlist
        	Master Cell Name:	level3
        	NumBits:		1
        ModInstTerm:
        	Net:	scalar1
        	Inst:	I1
	Posit:	0 (bound to 'l3_in')
        ModInstTerm:
        	Net:	scalar2
        	Inst:	I2
	Posit:	0 (bound to 'l3_in')
        ModInstTerm:
        	Net:	scalar3
        	Inst:	I3
	Posit:	0 (bound to 'l3_in')
        ModInstTerm:
        	Net:	bus1[1:0]
        	Inst:	I1
	Posit:	1 (bound to 'l3_out[1:0]')
        ModInstTerm:
        	Net:	bus2[1:0]
        	Inst:	I2
	Posit:	1 (bound to 'l3_out[1:0]')
        ModInstTerm:
        	Net:	bus3[1:0]
        	Inst:	I3
	Posit:	1 (bound to 'l3_out[1:0]')



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Info: The top module is top
Contents of hier_designEMH.top.netlist
    Contents of module level1
            Term: 'l1_out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'l1_out'
        	Position:	1
            Term: 'l1_in[7:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	8
        	Net:		'l1_in[7:0]'
        	Position:	0
            Net: 'l1_out' (ModScalarNet)
            Net: 'l1_in[7:0]' (ModBusNet)
    Contents of module level2A
            Term: 'l2A_out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'l2A_out'
        	Position:	1
            Term: 'l2A_in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'l2A_in'
        	Position:	0
            Net: 'l2A_busReg[7:0]' (ModBusNet)
            Net: 'l2A_out' (ModScalarNet)
            Net: 'l2A_in' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	l2A_busReg[7:0]
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[7:0]')
        ModInstTerm:
        	Net:	l2A_out
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
    Contents of module level2B
            Term: 'l2B_out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'l2B_out[1:0]'
        	Position:	1
            Term: 'l2B_in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'l2B_in'
        	Position:	0
            Net: 'l2B_busReg[7:0]' (ModBusNet)
            Net: 'l2B_out[1]' (ModBusNetBit)
            Net: 'l2B_out[1:0]' (ModBusNet)
            Net: 'l2B_in' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	l2B_busReg[7:0]
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[7:0]')
        ModInstTerm:
        	Net:	l2B_out[1]
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
    Contents of module level3
            Term: 'l3_out[1:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	2
        	Net:		'l3_out[1:0]'
        	Position:	1
            Term: 'l3_in' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'l3_in'
        	Position:	0
            Net: 'l3_out[1]' (ModBusNetBit)
            Net: 'l3_out[1:0]' (ModBusNet)
            Net: 'l3_in' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I2B
        	Master Cell Name:	level2B
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I1A
        	Master Cell Name:	level2A
        	NumBits:		1
        ModInstTerm:
        	Net:	l3_out[1]
        	Inst:	I1A
	Posit:	1 (bound to 'l2A_out')
        ModInstTerm:
        	Net:	l3_out[1:0]
        	Inst:	I2B
	Posit:	1 (bound to 'l2B_out[1:0]')
        ModInstTerm:
        	Net:	l3_in
        	Inst:	I2B
	Posit:	0 (bound to 'l2B_in')
        ModInstTerm:
        	Net:	l3_in
        	Inst:	I1A
	Posit:	0 (bound to 'l2A_in')
    Contents of TOP module top
            Net: 'bus3[1:0]' (ModBusNet)
            Net: 'bus2[1:0]' (ModBusNet)
            Net: 'bus1[1:0]' (ModBusNet)
            Net: 'scalar3' (ModScalarNet)
            Net: 'scalar2' (ModScalarNet)
            Net: 'scalar1' (ModScalarNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I3
        	Master Cell Name:	level3
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I2
        	Master Cell Name:	level3
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level3
        	NumBits:		1
        ModInstTerm:
        	Net:	bus3[1:0]
        	Inst:	I3
	Posit:	1 (bound to 'l3_out[1:0]')
        ModInstTerm:
        	Net:	bus2[1:0]
        	Inst:	I2
	Posit:	1 (bound to 'l3_out[1:0]')
        ModInstTerm:
        	Net:	bus1[1:0]
        	Inst:	I1
	Posit:	1 (bound to 'l3_out[1:0]')
        ModInstTerm:
        	Net:	scalar3
        	Inst:	I3
	Posit:	0 (bound to 'l3_in')
        ModInstTerm:
        	Net:	scalar2
        	Inst:	I2
	Posit:	0 (bound to 'l3_in')
        ModInstTerm:
        	Net:	scalar1
        	Inst:	I1
	Posit:	0 (bound to 'l3_in')



Reader succeeded