inouttest.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module bottom (
    v,
    w,
    x,
    y,
    z);

    inout v;
    inout w;
    inout x;
    inout [1:0] y;
    inout [1:0] z;

endmodule // bottom


module top (
    v,
    w,
    x,
    y,
    z);

    inout v;
    inout w;
    inout x;
    inout [1:0] y;
    inout [1:0] z;

    wire [1:0] e;
    wire [1:0] d;
    wire c;
    wire b;
    wire a;

    bottom named (
            .v(a),
            .w(b),
            .x(c),
            .y(d),
            .z(e));
    bottom order (
            .v(a),
            .w(b),
            .x(c),
            .y(d),
            .z(e));
endmodule // top