arrayinst.v

openaccess与verilog互相转化时所用的源代码

// Test connections to vector instances

module dff(output out, input in, input rst, input clk);
endmodule

module oneBit();
    dff r[0] (a, b, c, d);
endmodule

module byName(output [7:0] Q, input [7:0] D, input clear, input clock);
    dff r[7:0] (.in(D), .out(Q), .rst(clear), .clk(clock));
endmodule

module byOrder(output [7:0] Q, input [7:0] D, input clear, input clock);
    dff r[7:0] (Q, D, clock, clear);
endmodule

module top;
    wire [15:0] a, b, c, d;
    wire A, B, C, D, E, F, G, H, J, K, P, Q, X, Y;
    wire [7:0] bx, by;
    
    byName  name[1:0]   (.Q(a), .D(b), .clear(P), .clock(Q));
    byName  name2[1:0]	(.Q(bx), .D(by), .clear(P), .clock(Q));
    byOrder order[1:0]  (c, d, X, Y);
    byOrder order2[1:0] (bx, by, X, Y);
    byOrder bundle[1:0] ({2{A,B,C,D,E,F,G,H}}, {2{A,B,C,D,E,F,G,H}}, J, K);
    
    leafCell name3[3:0] (.in(A), .out(bx));
    leafCell order3[3:0] (A, bx);
endmodule