oaverilogannotatetest.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogAnnotateTest.cpp
//
// This file contains the implementation of the	oaVerilogAnnotateTest class.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this	material may not be copied, modified,
// re-published, uploaded, executed, or	istributed in any way, in any medium,
// in whole or in part,	without	prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design	Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: sailajad $
//  $Revision: 1.21 $
//  $Date: 2005/08/05 21:58:13 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogInTest.h"



// *****************************************************************************
// oaVerilogAnnotateTest::oaVerilogAnnotateTest()
//
// This is the constructor for the oaVerilogAnnotateTest class.
// *****************************************************************************
oaVerilogAnnotateTest::oaVerilogAnnotateTest(const oaString &name,
					     oaBoolean	    trace)
:   oaVerilogInLeafTest(name, false, true, trace)
{
}



// *****************************************************************************
// oaVerilogAnnotateTest::test()
//
// This method is the main entry point for the test.
// *****************************************************************************
oaBoolean
oaVerilogAnnotateTest::test()
{
    preTest();

    oaString	firstLib("annotateLibA");
    oaString	secondLib("annotateLibB");

    buildLeafLib(firstLib, "noOrderHasTop", "wrong", false, true);
    buildLeafLib(firstLib, "noOrderHasTop", "right", false, true);
    buildLeafLib(firstLib, "hasOrderNoTop", "wrong");
    buildLeafLib(firstLib, "hasOrderNoTop", "right", true, false, false);
    buildLeafLib(secondLib, "noOrderNoTop", "wrong", false, true, false);
    buildLeafLib(secondLib, "noOrderNoTop", "right", false, true, false);
    makeCustomData(secondLib, "noDirection", "right");

    openOutputFile();
    enableCallbacks(true);

    try	{
	oaString    testcase = getPathToData() + ds + getName() + ".v";

	tout.print(starLine);
	tout.print("* Annotate\n");
	tout.print(starLine);

	oaNativeNS  ns;
	oaString    myLibName = getName();

	cleanup(myLibName);
	openLib(myLibName);

	MsgAdapter  msgs;

	msgs.setOutFile(tout.outFile);
	msgs.setLogFile(NULL);

	VerilogIn   reader(msgs);
	OptionsIn   &readerOptions = reader.getOptions();
	oaString    topModuleName("top");
	Annotate    annotate(reader.getScanner(), readerOptions);

	reader.setCallbacks(annotate);

	readerOptions.setTopModuleName(topModuleName);
	readerOptions.enableTolerate();
	readerOptions.enableFileAndLine(false);
	readerOptions.addLeafLib(firstLib);
	readerOptions.addLeafLib(secondLib);
	readerOptions.addLeafView("right");
	readerOptions.addLeafView("wrong");
	readerOptions.addFile(testcase);
	readerOptions.setLibName(myLibName);
	readerOptions.enableTopWarning(false);
	reader.parse();

	tout.print("Annotater succeeded\n\n\n\n");

	oaIter<oaDesign>    designIter(oaDesign::getOpenDesigns());

	while (oaDesign *d = designIter.getNext()) {
	    d->purge();
	}

	verilogWriteLib(firstLib, "temp.v");
	verilogWriteLib(secondLib, "temp.v");
    }
    catch (Error    &verr) {
	tout.print(verr.getMsg());
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }
    catch (oaException	 &oaErr) {
	tout.print((const char*) oaErr.getMsg());
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }
    catch (...) {
	tout.print("Caught an exception that was not handled by the reader.\n");
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }

    closeOutputFile();
    enableCallbacks(false);
    cleanup(firstLib);
    cleanup(secondLib);
    cleanup(getName());

    return compareOutputByName(getName());
}



// *****************************************************************************
// oaVerilogAnnotateTest::makeCustomData()
//
// This method creates a custom design for this test.  The design that it builds
// contains a module that has bus terms but no bit order on either the terms or
// the nets they are connected to.
// *****************************************************************************
void
oaVerilogAnnotateTest::makeCustomData(const oaString	&libPath,
				      const oaString	&cellNameStr,
				      const oaString	&viewNameStr)
{
    oaNativeNS	    ns;
    oaScalarName    leafLibName(ns, libPath);
    oaScalarName    leafCellName(ns, cellNameStr);
    oaScalarName    leafViewName(ns, viewNameStr);

    oaLib   *lib = oaLib::find(leafLibName);

    if (!lib && oaLib::exists(libPath)) {
	lib = oaLib::open(leafLibName, libPath);
    }

    if (!lib) {
	lib = oaLib::create(leafLibName, libPath);

	oaTech	*tech = oaTech::create(lib);
    
	tech->setDBUPerUU(oaViewType::get(oacMaskLayout), 1000);
	tech->save();
	tech->close();
    }

    if (oaDesign::find(leafLibName, leafCellName, leafViewName)) {
	return;
    }

    oaDesign	*design = oaDesign::open(leafLibName, leafCellName,	
					 leafViewName, 
                                         oaViewType::get(oacNetlist), 'w');
    oaModule	*module = oaModule::create(design, leafCellName);

    
    design->setTopModule(module);

    oaVectorBitName in0(ns, "in[0]");
    oaModBitNet	    *net0 = oaModBusNetBit::create(module, in0);
    oaModTerm	    *term0 = oaModBusTermBit::create(net0, in0, 
						     oacInputTermType);
    oaVectorBitName in1(ns, "in[1]");
    oaModBitNet	    *net1 = oaModBusNetBit::create(module, in1);
    oaModTerm	    *term1 = oaModBusTermBit::create(net1, in1, 
						     oacInputTermType);

    oaVectorName    out(ns, "out[0:1]");

    oaModTerm::create(oaModNet::create(module, out), out, 
		      oacOutputTermType);

    oaScalarName    inc(ns, "inconsistent");

    oaModTerm::create(oaModNet::create(module, inc), inc, 
		      oacInputOutputTermType);

    design->save();


    // This design creates several multi-bit terms but only individual bits are 
    // mentioned in the Verilog interface.
    design = oaDesign::open(leafLibName, oaScalarName(ns, "bitMember"),
			    leafViewName, oaViewType::get(oacMaskLayout), 'w');
    oaBlock *b = oaBlock::create(design);
    
    oaTerm::create(oaNet::create(b, oaName(ns, "a[0:1]")), oaName(ns, "a[0:1]"));
    oaTerm::create(oaNet::create(b, oaName(ns, "b[0:3]")), oaName(ns, "b[0:3]"));
    oaTerm::create(oaNet::create(b, oaName(ns, "c,d")), oaName(ns, "c,d"));

    design->save();


    // This design's top module's name is not the same as the cell name of the 
    // design.
    design = oaDesign::open(leafLibName, oaScalarName(ns, "inconsistentTop"),
			    leafViewName, oaViewType::get(oacMaskLayout), 'w');
    module = oaModule::create(design, oaScalarName(ns, "unexpectedTop"));
    design->setTopModule(module);
    oaModTerm::create(oaModNet::create(module, oaName(ns, "a")), 
		      oaName(ns, "a"));
    design->save();

    // This design has no modules at all.
    design = oaDesign::open(leafLibName, oaScalarName(ns, "noModules"),
			    leafViewName, oaViewType::get(oacMaskLayout), 'w');
    design->save();
}



// *****************************************************************************
// oaVerilogAnnotateTest::verilogWriteLib()
//
// This method uses the Verilog writer to dump the contents of the given
// library to the test output file.
// *****************************************************************************
void
oaVerilogAnnotateTest::verilogWriteLib(const oaString	&libNameStr,
				       const oaString	&outFile)
{
    MsgAdapter	    msgs;
    VerilogOut	    writer(msgs);
    OptionsOut	    &writerOptions = writer.getOptions();
    oaScalarName    myLibName(vns, libNameStr);
    oaLib	    *lib = oaLib::find(myLibName);

    if (!lib) {
	tout.printLine("Library %s was not found\n",
		       (const char*) libNameStr);
	return;
    }

    tout.printLine(starLine);
    tout.printLine("Dumping contents of library %s\n",
		   (const char*) libNameStr);
    tout.printLine(starLine);

    writerOptions.setLibName(libNameStr);
    writerOptions.setFileName((const char*) outFile);
    writerOptions.enableRecursive(true);

    lib->getAccess(oacWriteLibAccess);

    oaIter<oaCellView>	cvIter(lib->getCellViews());
    oaString		cellName;
    oaString		viewName;

    while (oaCellView *cv = cvIter.getNext()) {
	cv->getCell()->getName(vns, cellName);
	cv->getView()->getName(vns, viewName);

	if (cv->getPrimary() && cv->getPrimary()->existsOnDisk()) {
	    writerOptions.setCellName(cellName);
	    writerOptions.setViewName(viewName);

	    try {
		writer.write();

		FILE    *fp = fopen((const char*) outFile, "r");

		if (fp) {
		    char buf[128];

		    while (fgets(buf, 127, fp)) {
			tout.printLine(buf);
		    }

		    fclose(fp);
		    unlink((const char*) outFile);
		} else {
		    tout.printLine("Unable to open %s output file\n", 
				   (const char*) outFile);
		}
	    }
	    catch (Error &err) {
		tout.printLine("%s\n", (const char*) err.getMsg());
	    }
	}
    }
    lib->releaseAccess();
}