oaverilogannotate.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogAnnotate.cpp
//
// This file contains the implementation of the Annotate class.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or istributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.21 $
//  $Date: 2005/07/30 07:06:41 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogInPvt.h"

BEGIN_VERILOG_NAMESPACE



// *****************************************************************************
// Annotate::Annotate()
//
// This is the constructor for the Annotate class it takes a reference to a
// Scanner and an OptionsIn class as inputs.
// *****************************************************************************
Annotate::Annotate(const Scanner    &scanIn,
		   OptionsIn	    &optIn) 
: ModuleCallbacksIn(scanIn, optIn)
{
}



// *****************************************************************************
// Annotate::~Annotate()
//
// This is the destructor for the Annotate class.
// *****************************************************************************
Annotate::~Annotate()
{
}



// *****************************************************************************
// Annotate::init()
//
// This function initializes the callbacks. It must be called before parsing
// takes place.
// *****************************************************************************
void
Annotate::init()
{
    CallbacksIn::init();
}



// *****************************************************************************
// Annotate::all()
//
// This function is called at the end of the Verilog input.
// *****************************************************************************
void
Annotate::all()
{
    closeAllDesigns();
}



// *****************************************************************************
// Annotate::beginModule()
//
// This function is called when a new module definition is found. The input
// string "name" identifies the name of the new module.  This function creates
// a new design for the given Verilog module if the module name is not the name
// of a leaf cell.  The cell name of the design is the Verilog module name.
// If the design already exists, the current module is set to the top module
// of the design.  If there is no top module, then the top module will be
// detected.  If there is no module at all, then one is created and set as the
// top module.  A warning message is produced if the name of the top module of
// the leaf design does not match the name of the Verilog module.
// *****************************************************************************
void
Annotate::beginModule(const oaString	&name)
{
    currentModuleName.init(vns, name);
    
    oaDesign	*design = leafMgr.findLeaf(currentModuleName);

    isLeaf = leafMgr.isLeaf(currentModuleName);

    if (isLeaf) {
	currentDesign = design;
	currentDesign->reopen('a');
	currentModule = design->getTopModule();
	
	if (!currentModule) {
	    if (design->getModules().isEmpty()) {
		currentModule = oaModule::create(design, currentModuleName);
		design->setTopModule(currentModule);
	    } else {
		currentModule = detectTopModule();
		design->setTopModule(currentModule);
	    }
	}

	oaString    currentModuleNameStr;

	currentModule->getName(currentModuleName);
	currentModuleName.get(vns, currentModuleNameStr);
	currentModuleType = leafMgr.getType(currentModuleName);

	if (currentModuleNameStr != name) {
	    currentModuleType = ModuleIncompleteLeafType;
	    leafMgr.setType(currentModuleName, currentModuleType);

	    oaString	libNameStr;
	    oaString	cellNameStr;
	    oaString	viewNameStr;

	    design->getLibName(vns, libNameStr);
	    design->getCellName(vns, cellNameStr);
	    design->getViewName(vns, viewNameStr);

	    Error msg(TopModuleNameMismatch, fileAndLine, (const char*) name, 
		      (const char*) libNameStr, (const char*) cellNameStr, 
		      (const char*) viewNameStr, 
		      (const char*) currentModuleNameStr);

	    warning(msg);
	}	      
    } else {
	warning(Error(CellNotFound, fileAndLine, (const char*) name));
    } 

    currentParams.clear();
}



// *****************************************************************************
// Annotate::endModule()
//
// This function is called for each ENDMODULE token.  Port order is established
// and the current design is saved.
// *****************************************************************************
void
Annotate::endModule(const ParamList *ports,
		    const ParamList *portParams)
{
    if (!isLeaf) {
	return;
    }
    
    if (ports) {
	ModuleTypeEnum	leafType = currentModuleType;
	oaScalarName	cellName;

	currentModule->getName(cellName);

	clearPortOrder(currentModule);
	establishPortOrder(*ports, portParams);

	if (leafType != ModuleCellType) {
	    leafMgr.setType(currentModuleName, ModuleLeafType);
	    currentModuleType = ModuleLeafType;
	}
    }

    if (isLeaf && currentDesign->isModified()) {
	currentDesign->save();
    }

    currentDesign = NULL;
    currentModule = NULL;
    currentModuleType = ModuleUnknownType;
}



// *****************************************************************************
// Annotate::moduleInstance()
//
// This function is called for each module instantiation in a module 
// definition. Since the Annotation class should only modify the interface to
// modules and not the body or connectivity of the modules, this method does
// nothing except copy the instNameIn to the instNameOut.
// *****************************************************************************
void
Annotate::moduleInstance(const oaString	    &instMasterN,
			 const ParamList    &parameterL,
			 const oaName	    &instNameIn)
{
}



// *****************************************************************************
// Annotate::netDeclAssign()
//
// This function is called for a set of net declaration assignments.  Since the 
// Annotation class should only modify the interface to modules and not the
// body or connectivity of the modules, this method does nothing.
// *****************************************************************************
void
Annotate::netDeclAssign(const oaSigTypeEnum netType,
			const oaString	    *driveStrOpt,
			const oaString	    *signedOption,
			const Range	    *rangeOption,
			const ParamList	    *delayOption,
			const ParamList	    &netAssigns)
{
}



// *****************************************************************************
// Annotate::portDeclaration()
//
// This function is called for each port in a portDeclaration.  The portID is 
// the name of the terminal. If the portID is a scalar name, it may be modified
// by the range option to create a bus or bus bit. The signed option is ignored
// in the base callback implementation, however a derived class can use it to
// modify the creation of the term.  Normally, this function simply sets the
// term type.  However, if this function is called in the 2001 syntax, then the
// create flag will be true and a terminal may be created for the portID.
// *****************************************************************************
void
Annotate::portDeclaration(const	oaTermType	termType,
			  const	oaSigTypeEnum	netType,
			  const	oaString	*signedOpt,
			  const	Range		*rangeOpt,
			  const	oaName		&portID)
{
    if (!isLeaf) {
	return;
    }

    if (portID.getType() == oacScalarNameType && rangeOpt) {
	oaBitOrder  order = oacDescendingBitOrder;
	
	if (rangeOpt->getStartInt() < rangeOpt->getStopInt()) {
	    order = oacAscendingBitOrder;
	}

	oaModBusTermDef	*termDef = oaModBusTermDef::find(currentModule,
							 *portID.getScalar());

	if (termDef) {
	    if (termDef->isImplicit()) {
		termDef = oaModBusTermDef::create(currentModule, 
						  *portID.getScalar(), order);
	    }

	    if (termDef->getBitOrder() != order) {
		termDef->setBitOrder(order);
	    }

	    oaModBusNetDef  *netDef = oaModBusNetDef::find(currentModule, 
							   *portID.getScalar());

	    if (!netDef || netDef->isImplicit()) {
		netDef = oaModBusNetDef::create(currentModule, 
						*portID.getScalar(), order);
	    }

	    if (netDef->getBitOrder() != order) {
		netDef->setBitOrder(order);
	    }
	}
    }
    
    CallbacksIn::portDeclaration(termType, netType, signedOpt, rangeOpt, 
				 portID);
}



// *****************************************************************************
// Annotate::clearPortOrder()
//
// This function removes the position and isInterface information from all the 
// terminals in the module.
// *****************************************************************************
void
Annotate::clearPortOrder(oaModule   *module)
{
    oaIter<oaModTerm>	termIter(module->getTerms());

    while (oaModTerm *term = termIter.getNext()) {
	term->unsetPosition();
	term->setIsInterface(false);
    }
}



END_VERILOG_NAMESPACE