oaverilogcallbacksin.h

openaccess与verilog互相转化时所用的源代码

    virtual void	    closeDesign(oaDesign    *design,
				        oaBoolean   purge = false);
    virtual void	    expandCreateInstTerm(oaModVectorInst    *inst,
						 oaModNet	    *net,
						 oaName		    &termName);
    virtual void	    expandCreateInstTerm(oaModVectorInst    *inst,
						 oaModNet	    *net,
						 oaUInt4	    termPos);
    virtual void	    expandITermScalarName(const	oaScalarName	&in,
						  const oaModNet	&net,
						  const	oaModInst	&inst,
						  oaName		&out);
    virtual void	    expandNetBundleName(const oaBundleName  &in,
						oaBundleName	    &out);
    virtual void	    expandNetScalarName(const oaScalarName  &in,
						const Range *range,
						oaName	    &out);
    virtual void	    expandTermBundleName(const oaBundleName &in,
						 oaBundleName	    &out);
    virtual void	    expandTermScalarName(const oaScalarName &in,
						 oaName		    &out);
    virtual oaModInst	    *findInst(const oaName  &instName);
    virtual void	    fixStubRefs();
    virtual void	    fixInstTerms(oaModInst  *inst);
    virtual oaTermType	    genTermType(const oaName	    &termName,
					const oaTermType    requestedType,
					const oaModNet	    *net);
    virtual oaModBitNet	    *getExplicitBit(oaModNet	*net, 
					    oaUInt4	index);
    virtual oaModTerm	    *getExplicitBit(oaModTerm	*term, 
					    oaUInt4	index);
    virtual oaModInst	    *getInst(const oaString	&instMasterN,
				     const ParamList	&parameterL,
				     const oaName	&instName);
    virtual oaModScalarInst *getInst(const oaScalarName	&libName,
				     const oaScalarName	&cellName,
				     const oaScalarName	&viewName,
				     const oaScalarName	&instName);
    virtual oaModVectorInst *getInst(const oaScalarName	&libName,
				     const oaScalarName	&cellName,
				     const oaScalarName	&viewName,
				     const oaVectorName	&instName);
    virtual oaModVectorInstBit *getInst(const oaScalarName	&libName,
					const oaScalarName	&cellName,
					const oaScalarName	&viewName,
					const oaVectorBitName	&instName);
    virtual void	    getModAndNetName(const oaName   &name,
					     oaScalarName   &moduleName,
					     oaName	    &netName);
    virtual oaModNet	    *getNet(const oaName	&name,
				    const oaSigTypeEnum	requestedType,
				    const oaString	*signedOpt,
				    const Range		*rangeOpt,
				    const oaBoolean	warn);
    virtual oaModBundleNet  *getNet(const oaBundleName	&name,
				    const oaSigTypeEnum	netType,
				    const oaString	*signedOpt,
				    const oaBoolean	warn);
    virtual oaModNet	    *getNet(const oaScalarName	&name,
				    const oaSigTypeEnum	netType,
				    const oaString	*signedOpt);
    virtual oaModBusNet	    *getNet(const oaVectorName	&name,
				    const oaSigTypeEnum	netType,
				    const oaString	*signedOpt);
    virtual oaModBusNetBit  *getNet(const oaVectorBitName   &name,
				    const oaSigTypeEnum	    netType,
				    const oaString	    *signedOpt);
    virtual oaModNet	    *getHierNet(const oaName	    &name,
					const oaSigTypeEnum requestedType,
					const oaString	    *signedOpt = NULL,
					const Range	    *rangeOpt = NULL,
					const oaBoolean	    warn = false);
    virtual oaModNet	    *getLocalNet(const oaName	    &name,
					const oaSigTypeEnum requestedType,
					const oaString	    *signedOpt = NULL,
					const Range	    *rangeOpt = NULL,
					oaBoolean	    global = false,
					const oaBoolean	    warn = false);
    virtual oaModTerm	    *getPort(const oaName	    &name,
				     const oaModNet	    *netIn,
				     oaTermType		    termType,
				     const oaSigTypeEnum    netType,
				     const oaString	    *signedOpt = NULL,
				     const Range	    *rangeOpt = NULL);
    virtual oaModBundleTerm *getPort(const oaBundleName	&name,
				     oaModNet		*&net,
				     const oaTermType	termType,
				     const oaString	*signedOpt);
    virtual oaModScalarTerm *getPort(const oaScalarName	&name,
				     oaModNet		*&net,
				     const oaTermType	termType,
				     const oaString	*signedOpt);
    virtual oaModBusTerm    *getPort(const oaVectorName	&name,
				     oaModNet		*&net,
				     const oaTermType	termType,
				     const oaString	*signedOpt);
    virtual oaModBusTermBit *getPort(const oaVectorBitName  &name,
				     oaModNet		    *&net,
				     const oaTermType	    termType,
				     const oaString	    *signedOpt);
    virtual oaTermType	    getTermType(const oaModNet	*net) const;
    virtual oaUInt4	    getRefCount(const oaModule	*module);
    virtual oaSigTypeEnum   getSigType(const oaName &name) const;
    virtual void	    getStartStopStep(const oaModBusNetDef   &bus,
					     oaUInt4		    &start,
					     oaUInt4		    &stop,
					     oaInt4		    &step);
    virtual void	    getStartStopStep(const oaModBusTermDef  &bus,
					     oaUInt4		    &start,
					     oaUInt4		    &stop,
					     oaInt4		    &step);
    virtual void	    getStartStopStep(const oaName   &name,
					     oaUInt4	    &start,
					     oaUInt4	    &stop,
					     oaInt4	    &step);
    virtual void	    getStartStopStep(const oaModNet &net,
					     oaUInt4	    &start,
					     oaUInt4	    &stop,
					     oaInt4	    &step);
    virtual oaBoolean	    getValueInt(const oaString	&paramName,
					oaInt4		&value);
    virtual void	    incRefCount(oaModule    *module);
    virtual oaBoolean	    isEmpty(const oaDesign  *design) const;
    virtual oaBoolean	    isEmpty(const oaModule  *module) const;
    virtual oaBoolean	    isStub(const oaScalarName	&cellName) const;
    virtual void	    makeUniqueNetName(const oaModule	*module,
					      const oaName	&nameIn,
					      oaName		&nameOut);
    virtual void	    makeUniqueTermName(const oaModule	*module,
					       const oaName	&nameIn,
					       oaName		&nameOut);
    virtual void	    moveToNet(oaModTerm	*&term,
				      oaModNet	&net);
    virtual void	    multiConcatToPrimary(ValueList  &concat,
						 Value	    &primary);
    virtual void	    netAssignment(oaName    &netNameA, 
					  oaName    &netNameB);
    virtual void	    rangeExprMsbLsb(const Value	&msb,
					    const Value	&lsb,
					    Range	&range);
    virtual void	    resolveNetHier(const oaName	&nameIn,
					   oaName	&nameOut,
					   oaBoolean	&isGlobal);
    virtual void	    resolveNetHier(const oaName	&nameIn,
					   oaSimpleName	&nameOut,
					   oaBoolean	&isGlobal);
    virtual void	    setRefCount(oaModule    *module,
					oaUInt4	    count);
    virtual void	    setTermType(oaModNet	    *net,
					const oaTermType    termType);
    virtual void	    validatePorts(const	ParamList   &ports,
					  const	ParamList   *params);
    virtual void	    warning(const Error	&msg);
    virtual void	    widthWarning(const oaModNet	*net,
					 const oaName	&termName);
    virtual void	    widthWarning(const oaModNet	    *net,
					 const oaModTerm    *term);

    OptionsIn		    &options;
    const Scanner	    &scanner;
    Scanner		    *fileAndLine;
    oaVerilogNS		    vns;
    oaLib		    *currentLibrary;
    oaDesign		    *currentDesign;
    oaModule		    *currentModule;
    oaScalarName	    currentModuleName;
    oaBoolean		    isLeaf;
    ParamList		    currentParams;
    oaIntAppDef<oaModule>   *refCount;
    LeafMgr		    leafMgr;
    oaModTerm		    *lastTerm;
    oaSimpleName	    tieHighNet;
    oaSimpleName	    tieLowNet;
    oaString		    tieHighNetNameStr;
    oaString		    tieLowNetNameStr;
    ModuleTypeEnum	    currentModuleType;
    oaScalarName	    tempDesignName;

    oaInterPointerAppDef<oaModNet>  *bundleMember;
    std::set<oaDesign*>	    openedDesigns;
    oaName		    expandedName;

    oaBooleanAppDef<oaDesign>	*modifiedBy;
    oaBooleanAppDef<oaDesign>	*designCreatedBy;
    oaBooleanAppDef<oaModTerm>	*termCreatedBy;
    oaIntAppDef<oaModNet>	*netTermType;

friend class OA_VERILOG_DLL_API	ParserBase;
friend class OA_VERILOG_DLL_API	Parser;
friend class OA_VERILOG_DLL_API	LeafMgr;
};



END_VERILOG_NAMESPACE

#endif