📄 oaverilogmodulecallbacksin.cpp
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CallbacksIn::expandCreateInstTerm(inst, net, termPos);}// *****************************************************************************// ModuleCallbacksIn::expandCreateInstTerm()//// The Verilog language allows single bit nets to connect to single bit terms// of multi-bit instances. These methods expand the single bit net to fit // the intended width of the connection when the connected instance is a // ModModuleVectorInst. The first function connnects by name. The second// function connects by position.// *****************************************************************************voidModuleCallbacksIn::expandCreateInstTerm(oaModModuleVectorInst *inst, oaModNet *net, oaName &termName){ if (net->getNumBits() == 1 && termName.getNumBits() == 1) { oaName nName; oaString nNameStr; net->getName(nName); nName.get(vns, nNameStr); oaSimpleName bitName(vns, nNameStr); oaBundleName bName(bitName, inst->getNumBits()); oaModBundleNet *bNet = oaModBundleNet::find(currentModule, bName); if (!bNet) { bNet = oaModBundleNet::create(currentModule, bName, net->getSigType(), net->isGlobal()); } createInstTerm(bNet, (oaModInst*) inst, termName); } else { createInstTerm(net, (oaModInst*) inst, termName); }}voidModuleCallbacksIn::expandCreateInstTerm(oaModModuleVectorInst *inst, oaModNet *net, oaUInt4 termPos){ if (net->getNumBits() == 1) { oaName nName; oaString nNameStr; net->getName(nName); nName.get(vns, nNameStr); oaSimpleName bitName(vns, nNameStr); oaBundleName bName(bitName, inst->getNumBits()); oaModBundleNet *bNet = oaModBundleNet::find(currentModule, bName); if (!bNet) { bNet = oaModBundleNet::create(currentModule, bName, net->getSigType(), net->isGlobal()); } createInstTerm(bNet, (oaModInst*) inst, termPos); } else { createInstTerm(net, (oaModInst*) inst, termPos); }}// *****************************************************************************// ModuleCallbacksIn::detachEmptyModules//// This function detaches all modules in the current design that are empty (as// defined by the CallbacksIn::isEmpty() method).// *****************************************************************************voidModuleCallbacksIn::detachEmptyModules(){ oaIter<oaModule> modIter(currentDesign->getModules()); const oaScalarName &libName = options.getLibName(); oaScalarName cellName; const oaScalarName &viewName = options.getFirstLeafView(); while (oaModule *module = modIter.getNext()) { if (isEmpty(module)) { module->getName(cellName); module->detach(libName, cellName, viewName); } }}// *****************************************************************************// ModuleCallbacksIn::detachStubs()//// This function converts all unbound module instances into unbound design// instances. The library name is the name of the current library, the cell// name is the name of the module and the view name is the first leaf view // name.// *****************************************************************************voidModuleCallbacksIn::detachStubs(){ oaLib *lib = currentDesign->getLib(); const oaScalarName &libName = options.getLibName(); oaScalarName cellName; const oaScalarName &viewName = options.getFirstLeafView(); StrHdrMapIter iter(&stubMap); HdrSet *hdrSet; oaString key; while (iter.getNext(key, hdrSet)) { cellName.init(vns, key); if (!oaModule::find(currentDesign, cellName)) { oaModule *stubM = oaModule::create(currentDesign, cellName); oaDesign *stubD = stubM->detach(libName, cellName, viewName); stubD->purge(); oaDesign::destroy(libName, cellName, viewName); } }}// *****************************************************************************// ModuleCallbacksIn::detectTopModule//// This function detects the top module based on the following criteria. First,// the top module is the module that has no other references to it within the // design (i.e.: there are no module instances of this module anywhere in the// design). Second, if multiple modules have no references, then the module// with the greatest hierarchical module depth is the top module. The term// "hierarchical module depth" refers to the number of levels of module// hierarchy that are all within the same design. Third, if the first two cases// are equal, then the top module is the module that appeared later in the// Verilog input.// *****************************************************************************oaModule*ModuleCallbacksIn::detectTopModule(){ oaGroup *topCandidates = oaGroup::create(currentDesign, options.getTopModuleGroupName()); selectUnreferencedModules(topCandidates); oaModule *top; if (topCandidates->getMembers().getCount() > 1) { selectDeepHierarchy(topCandidates); if (topCandidates->getMembers().getCount() > 1) { top = selectLatest(topCandidates); } else { oaIter<oaGroupMember> memIter(topCandidates->getMembers()); oaGroupMember *mem = memIter.getNext(); top = (oaModule*) mem->getObject(); } } else if (topCandidates->getMembers().getCount() == 1) { oaIter<oaGroupMember> memIter(topCandidates->getMembers()); oaGroupMember *mem = memIter.getNext(); top = (oaModule*) mem->getObject(); } else { top = NULL; } if (top) { oaString topModNameStr; top->getName(vns, topModNameStr); options.getMsgAdapter()->printInfo("Info: The top module is %s\n", (const char*) topModNameStr); } topCandidates->destroy(); return top;}// *****************************************************************************// ModuleCallbacksIn::findModuleInst()//// This function finds the instance with the given name in the current module.// This function may return implicit instances.// *****************************************************************************oaModModuleInst*ModuleCallbacksIn::findModuleInst(const oaName &instName){ switch (instName.getType()) { case oacScalarNameType: return oaModModuleScalarInst::find(currentModule, *instName.getScalar()); case oacVectorBitNameType: { oaScalarName base; oaUInt4 index; instName.getVectorBit()->getBaseName(base); index = instName.getVectorBit()->getIndex(); return oaModModuleVectorInstBit::find(currentModule, base, index); } case oacVectorNameType: { oaScalarName base; oaUInt4 start; oaUInt4 stop; oaInt4 step; instName.getVector()->getBaseName(base); getStartStopStep(instName, start, stop, step); return oaModModuleVectorInst::find(currentModule, base, start, stop); } default: { oaString nameStr; Options::oaNameToString(instName, nameStr); throw Error(InvalidInstName, fileAndLine, (const char*) nameStr); } }}// *****************************************************************************// ModuleCallbacksIn::fixStubRefs()//// This function converts design instances whose cell name matches the current// module's name, into module instances of the current module.// *****************************************************************************voidModuleCallbacksIn::fixStubRefs(){ oaString modNameStr; HdrSet *hdrs; currentModuleName.get(vns, modNameStr); stubMap.find(modNameStr, hdrs); for (HdrSetIter iter = hdrs->begin(); iter != hdrs->end(); iter++) { oaIter<oaModInst> instIter((*iter)->getInsts()); while (oaModInst *inst = instIter.getNext()) { fixInstTerms(inst); } } stubMap.remove(modNameStr); delete hdrs;}// *****************************************************************************// ModuleCallbacksIn::fixInstTerms()// ModuleCallbacksIn::fixInstTermsByName()// ModuleCallbacksIn::fixInstTermsByPosition()//// These functions fix the instTerms after the instance master has been // defined.// *****************************************************************************voidModuleCallbacksIn::fixInstTerms(oaModInst *inst){ if (!inst->usesTermPositions()) { fixInstTermsByName(inst); } else { fixInstTermsByPosition(inst); }}voidModuleCallbacksIn::fixInstTermsByName(oaModInst *inst){ oaName termName; oaScalarName baseName; oaIter<oaModInstTerm> itermIter(inst->getInstTerms()); while (oaModInstTerm *iterm = itermIter.getNext()) { if (iterm->isBound()) { continue; } iterm->getTermName(termName); if (termName.getType() == oacVectorNameType) { termName.getVector()->getBaseName(baseName); oaModule *master = inst->getMasterModule(); oaModBusTermDef *def = oaModBusTermDef::find(master, baseName); if (def) { oaUInt4 start; oaUInt4 stop; oaInt4 step; getStartStopStep(*def, start, stop, step); termName.getVector()->setStart(start); termName.getVector()->setStop(stop); } } oaModNet *net = iterm->getNet(); iterm->destroy(); createInstTerm(net, inst, termName); }}voidModuleCallbacksIn::fixInstTermsByPosition(oaModInst *inst){ oaIter<oaModInstTerm> itermIter(inst->getInstTerms()); while (oaModInstTerm *iterm = itermIter.getNext()) { if (iterm->isBound()) { continue; } oaUInt4 pos = iterm->getTermPosition(); oaModNet *net = iterm->getNet(); iterm->destroy(); createInstTerm(net, inst, pos); }}// *****************************************************************************// ModuleCallbacksIn::getModHierDepth()//// This function finds or computes the depth of the given module. The module's// depth is the maximum depth of all of the modules it instantiates plus// one. For example, a module with no module instances has a depth of 1. A// module that instantiates only modules with a depth of 1 has a depth of 2. A// module that instantiates a module with a depth of 5 and a depth of 7 has a // depth of 8.// *****************************************************************************oaUInt4ModuleCallbacksIn::getModHierDepth(oaModule *module){ if (moduleDepth->get(module) != INT_MAX) { return moduleDepth->get(module); } oaUInt4 maxDepth = 0; oaIter<oaModModuleInstHeader> ihdrIter(module->getModuleInstHeaders()); while (oaModModuleInstHeader *ihdr = ihdrIter.getNext()) { oaModule *master = ihdr->getMasterModule(); oaUInt4 depth = master ? getModHierDepth(master) : 1; if (depth > maxDepth) { maxDepth = depth; } } moduleDepth->set(module, maxDepth + 1); return maxDepth + 1;}// *****************************************************************************// ModuleCallbacksIn::getModuleInst()//// This function finds or creates the given instance identified by instName. The// parameter array is ignored in the base callback implementation, but it may// be used by a method in a derived callback class to modify the instance// creation. If the master refers to a leaf cell, or if the master module is // not found in the current design, then a design instance is created.// *****************************************************************************oaModInst*ModuleCallbacksIn::getModInst(const oaString &instMasterN, const ParamList ¶meterL, const oaName &instName){ oaScalarName libName; oaScalarName cellName(vns, instMasterN); oaScalarName viewName; oaDesign *design = leafMgr.findLeaf(cellName); oaModInst *inst = NULL; if (design) { design->getLibName(libName); design->getViewName(viewName); } else { oaModule *module = oaModule::find(currentDesign, cellName); if (module) { incRefCount(module); } } switch (instName.getType()) { case oacScalarNameType:
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