oaverilogmodulecallbacksin.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogModuleCallbacksIn.cpp
//
// This file contains the implementation of the ModuleCallbacksIn class
// callbacks.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or istributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.77 $
//  $Date: 2005/08/06 04:12:12 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogInPvt.h"



BEGIN_VERILOG_NAMESPACE
using namespace	std;



// *****************************************************************************
// ModuleCallbacksIn::ModuleCallbacksIn()
//
// This is the constructor for the ModuleCallbacksIn class it takes a
// reference to an Scanner and an oaVeriogInOption class as inputs.
// *****************************************************************************
ModuleCallbacksIn::ModuleCallbacksIn(const Scanner  &scanIn,
				     OptionsIn	    &optIn)	
:   CallbacksIn(scanIn, optIn)
{
    moduleIndex = (oaIntAppDef<oaModule>*) 
			oaIntAppDef<oaModule>::get(options.getModuleIndexName(),
						   0, false);
    moduleDepth = (oaIntAppDef<oaModule>*) 
			oaIntAppDef<oaModule>::get(options.getModuleDepthName(),
						   INT_MAX, false);
}



// *****************************************************************************
// ModuleCallbacksIn::~ModuleCallbacksIn()
//
// This is the destructor for the ModuleCallbacksIn class.
// *****************************************************************************
ModuleCallbacksIn::~ModuleCallbacksIn()
{
    currentModule = NULL;
}



// *****************************************************************************
// ModuleCallbacksIn::addStub()
//
// This function adds the given instHeader to the set of stub instHeaders that
// are associated with the given module name. Stub instHeaders are unbound
// instHeaders because the module is instantiated before it is defined.
// *****************************************************************************
void
ModuleCallbacksIn::addStub(const oaScalarName	    &moduleName,
			   oaModModuleInstHeader    *ihdr)
{
    oaString	modNameStr;
    HdrSet	*stubHdrs;

    moduleName.get(vns, modNameStr);

    if (stubMap.find(modNameStr, stubHdrs)) {
	stubHdrs->insert(ihdr);
    } else {
	stubHdrs = new HdrSet;
	stubHdrs->insert(ihdr);
	stubMap.insert(modNameStr, stubHdrs);
    }
}



// *****************************************************************************
// ModuleCallbacksIn::all()
//
// This function is called at end of parsing.  All modules that have no 
// references are removed from the design.  The top module is detected and set
// for the design.  The design is saved.
// *****************************************************************************
void
ModuleCallbacksIn::all()
{
    if (options.testBlackBoxEnabled()) {
	saveBlackBoxes();
    }

    oaModule	*top = setTopModule();

    detachStubs();
    pruneUnreferencedModules();
    checkUnresolved();

    if (currentDesign->isModified()) {
	oaString    cellNameStr;

	currentDesign->getCellName(vns, cellNameStr);

	oaScalarName	origName(vns, cellNameStr);

	if (cellNameStr == options.getTopModuleName()) {
	    currentDesign->save();
	} else {
	    oaScalarName    cellName;

	    if (options.getTopModuleName().isEmpty()) {
		top->getName(cellName);
	    } else {
		cellName.init(vns, options.getTopModuleName());
	    }

	    oaScalarName    viewName(options.getViewName());

	    if (!oaDesign::exists(options.getLibName(), cellName, viewName)
		|| options.testOverwriteEnabled()) {

		currentDesign->saveAs(options.getLibName(), cellName, viewName);

		if (!vns.isEqual(cellName, origName)) {
		    oaCellView	*dmCV = oaCellView::find(currentDesign->getLib(),
							 origName,viewName);
		    oaCell	*dmCell = dmCV->getCell();

		    closeDesign(currentDesign, true);
		    oaDesign::destroy(options.getLibName(), origName, viewName);
		    dmCV->destroy();
		    dmCell->destroy();
		    currentDesign = openDesign(options.getLibName(), cellName,	
					       viewName, 'a');
		}
	    } else {
		oaString    libNameStr;
		oaString    cellNameStr;
		oaString    viewNameStr;

		options.getLibName().get(vns, libNameStr);
		currentModuleName.get(vns, cellNameStr);
		viewName.get(vns, viewNameStr);

		throw Error(DesignExists, NULL, (const char*) libNameStr,
			    (const char*) cellNameStr, 
			    (const char*) viewNameStr);
	    }
	}		
    }

    currentDesign = NULL;

    oaIter<oaDesign>	designIter(oaDesign::getOpenDesigns());

    while (oaDesign *d = designIter.getNext()) {
	moduleIndex->remove(d);
	moduleDepth->remove(d);
    }

    StrHdrMapIter   iter(&stubMap);
    oaString	    key;
    HdrSet	    *hdrSet;

    while (iter.getNext(key, hdrSet)) {
	delete hdrSet;
    }
    
    stubMap.clear();

    closeAllDesigns();
}



// *****************************************************************************
// ModuleCallbacksIn::beginModule()
//
// This function is called when a new module definition is found.  The input
// string "name" identifies the name of the new module.  A new oaModule is
// created in the current design using the given module name.  If an oaModule
// with the given name already exists, it is destroyed.
// *****************************************************************************
void
ModuleCallbacksIn::beginModule(const oaString	&name)
{
    currentModuleName.init(vns, name);

    oaDesign	*design = leafMgr.findLeaf(currentModuleName);

    isLeaf = name != options.getTopModuleName() 
	     && leafMgr.isLeaf(currentModuleName);

    if (isLeaf) {
	currentModule = design->getTopModule();
	currentModuleType = leafMgr.getType(currentModuleName);
    } else {
	currentModule = oaModule::find(currentDesign,
				       currentModuleName);

	if (currentModule) {
	    currentModule->destroy();
	}

	currentModule = oaModule::create(currentDesign, currentModuleName);
	leafMgr.setType(currentModuleName, ModuleCellType);
	moduleIndex->set(currentModule, ++currentModuleIndex);
	currentModuleType = ModuleCellType;
    } 
}



// *****************************************************************************
// ModuleCallbacksIn::cleanModuleInterface()
//
// This function cleans the module interface. It removes terminals that do not
// have a position and which are not members of a bundle term.
// *****************************************************************************
void
ModuleCallbacksIn::cleanModuleInterface(oaModule    *module)
{
    oaIter<oaModTerm>	    termIter(module->getTerms());
    std::set<oaModTerm*>    bundleMembers;

    while (oaModTerm *term = termIter.getNext()) {
	if (term->getType() == oacModBundleTermType
	    && term->getPosition() != oacNullIndex) {
	    oaModBundleTerm	*bundle = (oaModBundleTerm*) term;
	    oaIter<oaModTerm>	memIter(bundle->getMembers());

	    while (oaModTerm *member = memIter.getNext()) {
		if (member->getType() == oacModBusTermBitType) {
		    oaModBusTermDef *def;
		    def = ((oaModBusTermBit*) member)->getDef();

		    oaIter<oaModBusTerm>    busIter(def->getBusTerms());

		    while (oaModBusTerm	*bus = busIter.getNext()) {
			bundleMembers.insert(bus);
		    }
		} else {
		    bundleMembers.insert(member);
		}
	    }
	}
    }

    termIter.reset();

    while (oaModTerm *term = termIter.getNext()) {
	if (term->getPosition() == oacNullIndex
	    && bundleMembers.find(term) == bundleMembers.end()) {
	    term->destroy();
	}
    }
}



// *****************************************************************************
// ModuleCallbacksIn::connectByName()
//
// Given an instance, a netName and an instTermName, this method establishes
// connectivity to the instance by name.
// *****************************************************************************
void
ModuleCallbacksIn::connectByName(const oaName	&instName,
				 const oaName	&netName,
				 const oaName	&instTermName)
{
    if (isLeaf) {
	return;
    }

    oaModModuleInst *inst = findModuleInst(instName);

    if (!inst) {
	CallbacksIn::connectByName(instName, netName, instTermName);
	return;
    }

    oaModNet	*net	= getNet(netName, oacSignalSigType, NULL, NULL, false);
    oaModule	*master	= inst->getMasterModule();
    oaName	termName;

    if (instTermName.getType() == oacScalarNameType) {
	expandITermScalarName(*instTermName.getScalar(), *net, *inst, termName);
    } else {
	termName = instTermName;
    }

    if (inst->getNumBits() > 1) {
	expandCreateInstTerm((oaModModuleVectorInst*) inst, net, termName);
    } else {
	createInstTerm(net, inst, termName);
    }
}



// *****************************************************************************
// ModuleCallbacksIn::connectByOrder()
//
// Given an instance and a list of port connections this method establishes
// connectivity to the instance by position.
//
// See CallbacksIn::connectByOrder for details.
// *****************************************************************************
void
ModuleCallbacksIn::connectByOrder(const	oaName	&instName,
				  const	oaName	&netName,
				  oaUInt4	&termPosition,
				  oaUInt4	bitPosition)
{
    if (isLeaf) {
	return;
    }

    oaModModuleInst *inst = findModuleInst(instName);

    if (!inst) {
	CallbacksIn::connectByOrder(instName, netName, termPosition, 
				    bitPosition);
	return;
    }

    oaModNet	*net = getNet(netName, oacSignalSigType, NULL, NULL, false);

    if (inst->getNumBits() > 1) {
	expandCreateInstTerm((oaModModuleVectorInst*) inst, net, termPosition);
    } else {
	createInstTerm(net, inst, termPosition);
    }
}



// *****************************************************************************
// ModuleCallbacksIn::endModule()
//
// This function is called for each ENDMODULE token. Terminal order is 
// established (or in the case of leaf cells, validated).
// *****************************************************************************
void
ModuleCallbacksIn::endModule(const ParamList	*ports,
			     const ParamList	*portParams)
{
    if (ports) {
	ModuleTypeEnum leafType = currentModuleType;

	if (leafType == ModuleStubType || leafType == ModuleIncompleteLeafType
	    || leafType == ModuleCellType) {
	    establishPortOrder(*ports, portParams);

	    if (leafType != ModuleCellType) {
		leafMgr.setType(currentModuleName, ModuleLeafType);
		currentModuleType = ModuleLeafType;
	    }
	} else {
	    validatePorts(*ports, portParams);
	}
    }

    cleanModuleInterface(currentModule);

    if (isStub(currentModuleName)) {
	fixStubRefs();
    }

    currentModule = NULL;
    currentModuleType = ModuleUnknownType;
}



// *****************************************************************************
// ModuleCallbacksIn::expandCreateInstTerm()
//
// The Verilog language allows single bit nets to connect to single bit terms
// of multi-bit instances. These methods expand the single bit net to fit 
// the intended width of the connection when the connected instance is a 
// ModVectorInst.  The first function connects by name.  The second function
// connects by position.
// *****************************************************************************
void
ModuleCallbacksIn::expandCreateInstTerm(oaModVectorInst	*inst,
					oaModNet	*net,
					oaName		&termName)
{
    CallbacksIn::expandCreateInstTerm(inst, net, termName);
}

void
ModuleCallbacksIn::expandCreateInstTerm(oaModVectorInst	*inst,
					oaModNet	*net,
					oaUInt4		termPos)
{